From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Alex Bennée" <alex.bennee@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: [PATCH v7 07/41] target/arm: Split out alle1_tlbmask
Date: Thu, 6 Feb 2020 10:54:14 +0000 [thread overview]
Message-ID: <20200206105448.4726-8-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200206105448.4726-1-richard.henderson@linaro.org>
No functional change, but unify code sequences.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v5: Do not confuse things by prefixing "vm".
---
target/arm/helper.c | 86 +++++++++++++--------------------------------
1 file changed, 24 insertions(+), 62 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8b3bb51dee..49da685b29 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3972,34 +3972,31 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
tlb_flush_by_mmuidx(cs, mask);
}
-static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t value)
+static int alle1_tlbmask(CPUARMState *env)
{
- /* Note that the 'ALL' scope must invalidate both stage 1 and
+ /*
+ * Note that the 'ALL' scope must invalidate both stage 1 and
* stage 2 translations, whereas most other scopes only invalidate
* stage 1 translations.
*/
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
-
if (arm_is_secure_below_el3(env)) {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
+ return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
+ } else if (arm_feature(env, ARM_FEATURE_EL2)) {
+ return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_S2NS;
} else {
- if (arm_feature(env, ARM_FEATURE_EL2)) {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
- ARMMMUIdxBit_S2NS);
- } else {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
}
}
+static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ CPUState *cs = env_cpu(env);
+ int mask = alle1_tlbmask(env);
+
+ tlb_flush_by_mmuidx(cs, mask);
+}
+
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4021,28 +4018,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- /* Note that the 'ALL' scope must invalidate both stage 1 and
- * stage 2 translations, whereas most other scopes only invalidate
- * stage 1 translations.
- */
CPUState *cs = env_cpu(env);
- bool sec = arm_is_secure_below_el3(env);
- bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
+ int mask = alle1_tlbmask(env);
- if (sec) {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else if (has_el2) {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
- ARMMMUIdxBit_S2NS);
- } else {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4092,20 +4071,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
- bool sec = arm_is_secure_below_el3(env);
+ CPUState *cs = env_cpu(env);
+ int mask = vae1_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
- if (sec) {
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
}
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4116,8 +4086,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
* since we don't support flush-for-specific-ASID-only or
* flush-last-level-only.
*/
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = vae1_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
if (tlb_force_broadcast(env)) {
@@ -4125,15 +4095,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
return;
}
- if (arm_is_secure_below_el3(env)) {
- tlb_flush_page_by_mmuidx(cs, pageaddr,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- tlb_flush_page_by_mmuidx(cs, pageaddr,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.20.1
next prev parent reply other threads:[~2020-02-06 10:57 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-06 10:54 [PATCH v7 00/41] target/arm: Implement ARMv8.1-VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 01/41] target/arm: Define isar_feature_aa64_vh Richard Henderson
2020-02-06 10:54 ` [PATCH v7 02/41] target/arm: Enable HCR_E2H for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 03/41] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2020-02-06 10:54 ` [PATCH v7 04/41] target/arm: Add TTBR1_EL2 Richard Henderson
2020-02-06 10:54 ` [PATCH v7 05/41] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 06/41] target/arm: Split out vae1_tlbmask Richard Henderson
2020-02-06 10:54 ` Richard Henderson [this message]
2020-02-06 10:54 ` [PATCH v7 08/41] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2020-02-06 10:54 ` [PATCH v7 09/41] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2020-02-06 10:54 ` [PATCH v7 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2020-02-06 10:54 ` [PATCH v7 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2020-02-06 10:54 ` [PATCH v7 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Richard Henderson
2020-02-06 10:54 ` [PATCH v7 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2020-02-06 10:54 ` [PATCH v7 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2020-02-06 10:54 ` [PATCH v7 15/41] target/arm: Recover 4 bits from TBFLAGs Richard Henderson
2020-02-06 10:54 ` [PATCH v7 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Richard Henderson
2020-02-06 10:54 ` [PATCH v7 17/41] target/arm: Rearrange ARMMMUIdxBit Richard Henderson
2020-02-06 10:54 ` [PATCH v7 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions Richard Henderson
2020-02-06 10:54 ` [PATCH v7 19/41] target/arm: Reorganize ARMMMUIdx Richard Henderson
2020-02-06 10:54 ` [PATCH v7 20/41] target/arm: Add regime_has_2_ranges Richard Henderson
2020-02-06 10:54 ` [PATCH v7 21/41] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 22/41] target/arm: Update arm_sctlr " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 23/41] target/arm: Update aa64_zva_access for EL2 Richard Henderson
2020-02-06 10:54 ` [PATCH v7 24/41] target/arm: Update ctr_el0_access " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 25/41] target/arm: Add the hypervisor virtual counter Richard Henderson
2020-02-06 10:54 ` [PATCH v7 26/41] target/arm: Update timer access for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 28/41] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2020-02-06 10:54 ` [PATCH v7 29/41] target/arm: Add VHE timer " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Richard Henderson
2020-02-06 10:54 ` [PATCH v7 31/41] target/arm: Flush tlbs for E2&0 " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 32/41] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 33/41] target/arm: Update {fp,sve}_exception_el for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 34/41] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2020-02-06 10:54 ` [PATCH v7 35/41] target/arm: Update get_a64_user_mem_index for VHE Richard Henderson
2020-02-06 10:54 ` [PATCH v7 36/41] target/arm: Update arm_cpu_do_interrupt_aarch64 " Richard Henderson
2020-02-06 10:54 ` [PATCH v7 37/41] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2020-02-06 10:54 ` [PATCH v7 38/41] target/arm: Move arm_excp_unmasked to cpu.c Richard Henderson
2020-02-06 10:54 ` [PATCH v7 39/41] target/arm: Pass more cpu state to arm_excp_unmasked Richard Henderson
2020-02-06 10:54 ` [PATCH v7 40/41] target/arm: Use bool for unmasked in arm_excp_unmasked Richard Henderson
2020-02-06 10:54 ` [PATCH v7 41/41] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Richard Henderson
2020-02-07 11:52 ` [PATCH v7 00/41] target/arm: Implement ARMv8.1-VHE Peter Maydell
2020-03-31 15:33 ` Jonathan Cameron
2020-03-31 17:29 ` Jonathan Cameron
2020-03-31 18:59 ` Richard Henderson
2020-04-01 10:45 ` Jonathan Cameron
2020-04-01 16:01 ` Jonathan Cameron
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