* [PATCH] i.MX: Fix inverted register bits in wdt code.
@ 2020-02-07 9:54 Roman Kapl
2020-02-11 17:57 ` Peter Maydell
0 siblings, 1 reply; 3+ messages in thread
From: Roman Kapl @ 2020-02-07 9:54 UTC (permalink / raw)
To: qemu-arm; +Cc: Peter Maydell, Roman Kapl, qemu-devel, Jean-Christophe Dubois
Documentation says for WDA '0: Assert WDOG output.' and for SRS
'0: Assert system reset signal.'.
Signed-off-by: Roman Kapl <rka@sysgo.com>
---
hw/misc/imx2_wdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/misc/imx2_wdt.c b/hw/misc/imx2_wdt.c
index e47e442592..c8944729c4 100644
--- a/hw/misc/imx2_wdt.c
+++ b/hw/misc/imx2_wdt.c
@@ -28,7 +28,7 @@ static void imx2_wdt_write(void *opaque, hwaddr addr,
uint64_t value, unsigned int size)
{
if (addr == IMX2_WDT_WCR &&
- (value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) {
+ (~value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) {
watchdog_perform_action();
}
}
--
2.22.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] i.MX: Fix inverted register bits in wdt code.
2020-02-07 9:54 [PATCH] i.MX: Fix inverted register bits in wdt code Roman Kapl
@ 2020-02-11 17:57 ` Peter Maydell
2020-02-12 9:10 ` Roman Kapl
0 siblings, 1 reply; 3+ messages in thread
From: Peter Maydell @ 2020-02-11 17:57 UTC (permalink / raw)
To: Roman Kapl; +Cc: qemu-arm, QEMU Developers, Jean-Christophe Dubois
On Fri, 7 Feb 2020 at 09:55, Roman Kapl <rka@sysgo.com> wrote:
>
> Documentation says for WDA '0: Assert WDOG output.' and for SRS
> '0: Assert system reset signal.'.
>
> Signed-off-by: Roman Kapl <rka@sysgo.com>
> ---
> hw/misc/imx2_wdt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to target-arm.next, thanks.
(It looks like we're missing a lot of the watchdog
functionality in our model, ie the actual watchdog
timer parts, enable bits, etc etc...)
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] i.MX: Fix inverted register bits in wdt code.
2020-02-11 17:57 ` Peter Maydell
@ 2020-02-12 9:10 ` Roman Kapl
0 siblings, 0 replies; 3+ messages in thread
From: Roman Kapl @ 2020-02-12 9:10 UTC (permalink / raw)
To: Peter Maydell, Roman Kapl
Cc: qemu-arm, QEMU Developers, Jean-Christophe Dubois
On 2/11/20 6:57 PM, Peter Maydell wrote:
> On Fri, 7 Feb 2020 at 09:55, Roman Kapl <rka@sysgo.com> wrote:
>>
>> Documentation says for WDA '0: Assert WDOG output.' and for SRS
>> '0: Assert system reset signal.'.
>>
>> Signed-off-by: Roman Kapl <rka@sysgo.com>
>> ---
>> hw/misc/imx2_wdt.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Applied to target-arm.next, thanks.
>
> (It looks like we're missing a lot of the watchdog
> functionality in our model, ie the actual watchdog
> timer parts, enable bits, etc etc...)
Yes, but the target restart functionality is the most important one. If
I've read the i.MX forums correctly it is the easiest way to restart the
board correctly.
Best regards, Roman Kapl
>
> -- PMM
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-02-12 9:12 UTC | newest]
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2020-02-07 9:54 [PATCH] i.MX: Fix inverted register bits in wdt code Roman Kapl
2020-02-11 17:57 ` Peter Maydell
2020-02-12 9:10 ` Roman Kapl
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