From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 12/48] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*
Date: Fri, 7 Feb 2020 14:33:07 +0000 [thread overview]
Message-ID: <20200207143343.30322-13-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
This is part of a reorganization to the set of mmu_idx.
The EL1&0 regime is the only one that uses 2-stage translation.
Spelling out Stage avoids confusion with Secure.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 6 +++---
target/arm/helper.c | 27 ++++++++++++++-------------
3 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c6da3d3043a..afc3e76ce50 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2923,8 +2923,8 @@ typedef enum ARMMMUIdx {
/* Indexes below here don't have TLBs and are used only for AT system
* instructions or for the first stage of an S12 page table walk.
*/
- ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB,
- ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB,
+ ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
+ ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
} ARMMMUIdx;
/* Bit macros for the core-mmu-index values for each index,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1509e45e98a..280b5b0c822 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -810,8 +810,8 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
switch (mmu_idx) {
case ARMMMUIdx_E10_0:
case ARMMMUIdx_E10_1:
- case ARMMMUIdx_S1NSE0:
- case ARMMMUIdx_S1NSE1:
+ case ARMMMUIdx_Stage1_E0:
+ case ARMMMUIdx_Stage1_E1:
case ARMMMUIdx_S1E2:
case ARMMMUIdx_Stage2:
case ARMMMUIdx_MPrivNegPri:
@@ -975,7 +975,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env);
#ifdef CONFIG_USER_ONLY
static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
{
- return ARMMMUIdx_S1NSE0;
+ return ARMMMUIdx_Stage1_E0;
}
#else
ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a6d4f449cc7..2d87c3a2e59 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3041,7 +3041,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
bool take_exc = false;
if (fi.s1ptw && current_el == 1 && !arm_is_secure(env)
- && (mmu_idx == ARMMMUIdx_S1NSE1 || mmu_idx == ARMMMUIdx_S1NSE0)) {
+ && (mmu_idx == ARMMMUIdx_Stage1_E1 ||
+ mmu_idx == ARMMMUIdx_Stage1_E0)) {
/*
* Synchronous stage 2 fault on an access made as part of the
* translation table walk for AT S1E0* or AT S1E1* insn
@@ -3189,10 +3190,10 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
mmu_idx = ARMMMUIdx_S1E3;
break;
case 2:
- mmu_idx = ARMMMUIdx_S1NSE1;
+ mmu_idx = ARMMMUIdx_Stage1_E1;
break;
case 1:
- mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
+ mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1;
break;
default:
g_assert_not_reached();
@@ -3205,10 +3206,10 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
mmu_idx = ARMMMUIdx_S1SE0;
break;
case 2:
- mmu_idx = ARMMMUIdx_S1NSE0;
+ mmu_idx = ARMMMUIdx_Stage1_E0;
break;
case 1:
- mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
+ mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0;
break;
default:
g_assert_not_reached();
@@ -3262,7 +3263,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
case 0:
switch (ri->opc1) {
case 0: /* AT S1E1R, AT S1E1W */
- mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
+ mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1;
break;
case 4: /* AT S1E2R, AT S1E2W */
mmu_idx = ARMMMUIdx_S1E2;
@@ -3275,7 +3276,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
}
break;
case 2: /* AT S1E0R, AT S1E0W */
- mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
+ mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0;
break;
case 4: /* AT S12E1R, AT S12E1W */
mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1;
@@ -8717,8 +8718,8 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
case ARMMMUIdx_S1SE0:
return arm_el_is_aa64(env, 3) ? 1 : 3;
case ARMMMUIdx_S1SE1:
- case ARMMMUIdx_S1NSE0:
- case ARMMMUIdx_S1NSE1:
+ case ARMMMUIdx_Stage1_E0:
+ case ARMMMUIdx_Stage1_E1:
case ARMMMUIdx_MPrivNegPri:
case ARMMMUIdx_MUserNegPri:
case ARMMMUIdx_MPriv:
@@ -8776,7 +8777,7 @@ static inline bool regime_translation_disabled(CPUARMState *env,
}
if ((env->cp15.hcr_el2 & HCR_DC) &&
- (mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1)) {
+ (mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1)) {
/* HCR.DC means SCTLR_EL1.M behaves as 0 */
return true;
}
@@ -8821,7 +8822,7 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
{
if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) {
- mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_E10_0);
+ mmu_idx += (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_E10_0);
}
return mmu_idx;
}
@@ -8856,7 +8857,7 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_S1SE0:
- case ARMMMUIdx_S1NSE0:
+ case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_MUser:
case ARMMMUIdx_MSUser:
case ARMMMUIdx_MUserNegPri:
@@ -9087,7 +9088,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
hwaddr addr, MemTxAttrs txattrs,
ARMMMUFaultInfo *fi)
{
- if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
+ if ((mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1) &&
!regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
target_ulong s2size;
hwaddr s2pa;
--
2.20.1
next prev parent reply other threads:[~2020-02-07 14:42 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-07 14:32 [PULL 00/48] target-arm queue Peter Maydell
2020-02-07 14:32 ` [PULL 01/48] target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none Peter Maydell
2020-02-07 14:32 ` [PULL 02/48] target/arm: Define isar_feature_aa64_vh Peter Maydell
2020-02-07 14:32 ` [PULL 03/48] target/arm: Enable HCR_E2H for VHE Peter Maydell
2020-02-07 14:32 ` [PULL 04/48] target/arm: Add CONTEXTIDR_EL2 Peter Maydell
2020-02-07 14:33 ` [PULL 05/48] target/arm: Add TTBR1_EL2 Peter Maydell
2020-02-07 14:33 ` [PULL 06/48] target/arm: Update CNTVCT_EL0 for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 07/48] target/arm: Split out vae1_tlbmask Peter Maydell
2020-02-07 14:33 ` [PULL 08/48] target/arm: Split out alle1_tlbmask Peter Maydell
2020-02-07 14:33 ` [PULL 09/48] target/arm: Simplify tlb_force_broadcast alternatives Peter Maydell
2020-02-07 14:33 ` [PULL 10/48] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Peter Maydell
2020-02-07 14:33 ` [PULL 11/48] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Peter Maydell
2020-02-07 14:33 ` Peter Maydell [this message]
2020-02-07 14:33 ` [PULL 13/48] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Peter Maydell
2020-02-07 14:33 ` [PULL 14/48] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Peter Maydell
2020-02-07 14:33 ` [PULL 15/48] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Peter Maydell
2020-02-07 14:33 ` [PULL 16/48] target/arm: Recover 4 bits from TBFLAGs Peter Maydell
2020-02-07 14:33 ` [PULL 17/48] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Peter Maydell
2020-02-07 14:33 ` [PULL 18/48] target/arm: Rearrange ARMMMUIdxBit Peter Maydell
2020-02-07 14:33 ` [PULL 19/48] target/arm: Tidy ARMMMUIdx m-profile definitions Peter Maydell
2020-02-07 14:33 ` [PULL 20/48] target/arm: Reorganize ARMMMUIdx Peter Maydell
2020-02-07 14:33 ` [PULL 21/48] target/arm: Add regime_has_2_ranges Peter Maydell
2020-02-07 14:33 ` [PULL 22/48] target/arm: Update arm_mmu_idx for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 23/48] target/arm: Update arm_sctlr " Peter Maydell
2020-02-07 14:33 ` [PULL 24/48] target/arm: Update aa64_zva_access for EL2 Peter Maydell
2020-02-07 14:33 ` [PULL 25/48] target/arm: Update ctr_el0_access " Peter Maydell
2020-02-07 14:33 ` [PULL 26/48] target/arm: Add the hypervisor virtual counter Peter Maydell
2020-02-07 14:33 ` [PULL 27/48] target/arm: Update timer access for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 28/48] target/arm: Update define_one_arm_cp_reg_with_opaque " Peter Maydell
2020-02-07 14:33 ` [PULL 29/48] target/arm: Add VHE system register redirection and aliasing Peter Maydell
2020-02-07 14:33 ` [PULL 30/48] target/arm: Add VHE timer " Peter Maydell
2020-02-07 14:33 ` [PULL 31/48] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Peter Maydell
2020-02-07 14:33 ` [PULL 32/48] target/arm: Flush tlbs for E2&0 " Peter Maydell
2020-02-07 14:33 ` [PULL 33/48] target/arm: Update arm_phys_excp_target_el for TGE Peter Maydell
2020-02-07 14:33 ` [PULL 34/48] target/arm: Update {fp,sve}_exception_el for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 35/48] target/arm: check TGE and E2H flags for EL0 pauth traps Peter Maydell
2020-02-07 14:33 ` [PULL 36/48] target/arm: Update get_a64_user_mem_index for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 37/48] target/arm: Update arm_cpu_do_interrupt_aarch64 " Peter Maydell
2020-02-07 14:33 ` [PULL 38/48] target/arm: Enable ARMv8.1-VHE in -cpu max Peter Maydell
2020-02-07 14:33 ` [PULL 39/48] target/arm: Move arm_excp_unmasked to cpu.c Peter Maydell
2020-02-07 14:33 ` [PULL 40/48] target/arm: Pass more cpu state to arm_excp_unmasked Peter Maydell
2020-02-07 14:33 ` [PULL 41/48] target/arm: Use bool for unmasked in arm_excp_unmasked Peter Maydell
2020-02-07 14:33 ` [PULL 42/48] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Peter Maydell
2020-02-07 14:33 ` [PULL 43/48] bcm2835_dma: Fix the ylen loop in TD mode Peter Maydell
2020-02-07 14:33 ` [PULL 44/48] bcm2835_dma: Re-initialize xlen " Peter Maydell
2020-02-07 14:33 ` [PULL 45/48] docs/arm-cpu-features: Make kvm-no-adjvtime comment clearer Peter Maydell
2020-02-07 14:33 ` [PULL 46/48] armv7m_systick: delay timer_new to avoid memleaks Peter Maydell
2020-02-07 14:33 ` [PULL 47/48] stm32f2xx_timer: " Peter Maydell
2020-02-07 14:33 ` [PULL 48/48] stellaris: " Peter Maydell
2020-02-10 12:06 ` [PULL 00/48] target-arm queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200207143343.30322-13-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).