From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 40/48] target/arm: Pass more cpu state to arm_excp_unmasked
Date: Fri, 7 Feb 2020 14:33:35 +0000 [thread overview]
Message-ID: <20200207143343.30322-41-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200207143343.30322-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Avoid redundant computation of cpu state by passing it in
from the caller, which has already computed it for itself.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200206105448.4726-40-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b81ed44bd2b..fcee0a2dd45 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -411,14 +411,13 @@ static void arm_cpu_reset(CPUState *s)
}
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
- unsigned int target_el)
+ unsigned int target_el,
+ unsigned int cur_el, bool secure,
+ uint64_t hcr_el2)
{
CPUARMState *env = cs->env_ptr;
- unsigned int cur_el = arm_current_el(env);
- bool secure = arm_is_secure(env);
bool pstate_unmasked;
int8_t unmasked = 0;
- uint64_t hcr_el2;
/*
* Don't take exceptions if they target a lower EL.
@@ -429,8 +428,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
return false;
}
- hcr_el2 = arm_hcr_el2_eff(env);
-
switch (excp_idx) {
case EXCP_FIQ:
pstate_unmasked = !(env->daif & PSTATE_F);
@@ -535,6 +532,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
CPUARMState *env = cs->env_ptr;
uint32_t cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
+ uint64_t hcr_el2 = arm_hcr_el2_eff(env);
uint32_t target_el;
uint32_t excp_idx;
bool ret = false;
@@ -542,7 +540,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_FIQ) {
excp_idx = EXCP_FIQ;
target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
cc->do_interrupt(cs);
@@ -552,7 +551,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_HARD) {
excp_idx = EXCP_IRQ;
target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
cc->do_interrupt(cs);
@@ -562,7 +562,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_VIRQ) {
excp_idx = EXCP_VIRQ;
target_el = 1;
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
cc->do_interrupt(cs);
@@ -572,7 +573,8 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
if (interrupt_request & CPU_INTERRUPT_VFIQ) {
excp_idx = EXCP_VFIQ;
target_el = 1;
- if (arm_excp_unmasked(cs, excp_idx, target_el)) {
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
cs->exception_index = excp_idx;
env->exception.target_el = target_el;
cc->do_interrupt(cs);
--
2.20.1
next prev parent reply other threads:[~2020-02-07 14:49 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-07 14:32 [PULL 00/48] target-arm queue Peter Maydell
2020-02-07 14:32 ` [PULL 01/48] target/arm/monitor: query-cpu-model-expansion crashed qemu when using machine type none Peter Maydell
2020-02-07 14:32 ` [PULL 02/48] target/arm: Define isar_feature_aa64_vh Peter Maydell
2020-02-07 14:32 ` [PULL 03/48] target/arm: Enable HCR_E2H for VHE Peter Maydell
2020-02-07 14:32 ` [PULL 04/48] target/arm: Add CONTEXTIDR_EL2 Peter Maydell
2020-02-07 14:33 ` [PULL 05/48] target/arm: Add TTBR1_EL2 Peter Maydell
2020-02-07 14:33 ` [PULL 06/48] target/arm: Update CNTVCT_EL0 for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 07/48] target/arm: Split out vae1_tlbmask Peter Maydell
2020-02-07 14:33 ` [PULL 08/48] target/arm: Split out alle1_tlbmask Peter Maydell
2020-02-07 14:33 ` [PULL 09/48] target/arm: Simplify tlb_force_broadcast alternatives Peter Maydell
2020-02-07 14:33 ` [PULL 10/48] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Peter Maydell
2020-02-07 14:33 ` [PULL 11/48] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Peter Maydell
2020-02-07 14:33 ` [PULL 12/48] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Peter Maydell
2020-02-07 14:33 ` [PULL 13/48] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] Peter Maydell
2020-02-07 14:33 ` [PULL 14/48] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Peter Maydell
2020-02-07 14:33 ` [PULL 15/48] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Peter Maydell
2020-02-07 14:33 ` [PULL 16/48] target/arm: Recover 4 bits from TBFLAGs Peter Maydell
2020-02-07 14:33 ` [PULL 17/48] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits Peter Maydell
2020-02-07 14:33 ` [PULL 18/48] target/arm: Rearrange ARMMMUIdxBit Peter Maydell
2020-02-07 14:33 ` [PULL 19/48] target/arm: Tidy ARMMMUIdx m-profile definitions Peter Maydell
2020-02-07 14:33 ` [PULL 20/48] target/arm: Reorganize ARMMMUIdx Peter Maydell
2020-02-07 14:33 ` [PULL 21/48] target/arm: Add regime_has_2_ranges Peter Maydell
2020-02-07 14:33 ` [PULL 22/48] target/arm: Update arm_mmu_idx for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 23/48] target/arm: Update arm_sctlr " Peter Maydell
2020-02-07 14:33 ` [PULL 24/48] target/arm: Update aa64_zva_access for EL2 Peter Maydell
2020-02-07 14:33 ` [PULL 25/48] target/arm: Update ctr_el0_access " Peter Maydell
2020-02-07 14:33 ` [PULL 26/48] target/arm: Add the hypervisor virtual counter Peter Maydell
2020-02-07 14:33 ` [PULL 27/48] target/arm: Update timer access for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 28/48] target/arm: Update define_one_arm_cp_reg_with_opaque " Peter Maydell
2020-02-07 14:33 ` [PULL 29/48] target/arm: Add VHE system register redirection and aliasing Peter Maydell
2020-02-07 14:33 ` [PULL 30/48] target/arm: Add VHE timer " Peter Maydell
2020-02-07 14:33 ` [PULL 31/48] target/arm: Flush tlb for ASID changes in EL2&0 translation regime Peter Maydell
2020-02-07 14:33 ` [PULL 32/48] target/arm: Flush tlbs for E2&0 " Peter Maydell
2020-02-07 14:33 ` [PULL 33/48] target/arm: Update arm_phys_excp_target_el for TGE Peter Maydell
2020-02-07 14:33 ` [PULL 34/48] target/arm: Update {fp,sve}_exception_el for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 35/48] target/arm: check TGE and E2H flags for EL0 pauth traps Peter Maydell
2020-02-07 14:33 ` [PULL 36/48] target/arm: Update get_a64_user_mem_index for VHE Peter Maydell
2020-02-07 14:33 ` [PULL 37/48] target/arm: Update arm_cpu_do_interrupt_aarch64 " Peter Maydell
2020-02-07 14:33 ` [PULL 38/48] target/arm: Enable ARMv8.1-VHE in -cpu max Peter Maydell
2020-02-07 14:33 ` [PULL 39/48] target/arm: Move arm_excp_unmasked to cpu.c Peter Maydell
2020-02-07 14:33 ` Peter Maydell [this message]
2020-02-07 14:33 ` [PULL 41/48] target/arm: Use bool for unmasked in arm_excp_unmasked Peter Maydell
2020-02-07 14:33 ` [PULL 42/48] target/arm: Raise only one interrupt in arm_cpu_exec_interrupt Peter Maydell
2020-02-07 14:33 ` [PULL 43/48] bcm2835_dma: Fix the ylen loop in TD mode Peter Maydell
2020-02-07 14:33 ` [PULL 44/48] bcm2835_dma: Re-initialize xlen " Peter Maydell
2020-02-07 14:33 ` [PULL 45/48] docs/arm-cpu-features: Make kvm-no-adjvtime comment clearer Peter Maydell
2020-02-07 14:33 ` [PULL 46/48] armv7m_systick: delay timer_new to avoid memleaks Peter Maydell
2020-02-07 14:33 ` [PULL 47/48] stm32f2xx_timer: " Peter Maydell
2020-02-07 14:33 ` [PULL 48/48] stellaris: " Peter Maydell
2020-02-10 12:06 ` [PULL 00/48] target-arm queue Peter Maydell
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