[PATCH v3 0/4] Add extra information to versioned CPU models

[PATCH v3 0/4] Add extra information to versioned CPU models

[Tao Xu]

This series of patches will remove MPX from Denverton, remove Remove
monitor from some CPU models. Add additional information for -cpu help
to indicate the changes in this version of CPU model.

The output is as follows:
./x86_64-softmmu/qemu-system-x86_64 -cpu help | grep "\["
x86 Broadwell-v2          Intel Core Processor (Broadwell) [no TSX]                 
x86 Broadwell-v3          Intel Core Processor (Broadwell) [IBRS]                   
x86 Broadwell-v4          Intel Core Processor (Broadwell) [no TSX, IBRS]           
x86 Cascadelake-Server-v2  Intel Xeon Processor (Cascadelake) [ARCH_CAPABILITIES]    
x86 Cascadelake-Server-v3  Intel Xeon Processor (Cascadelake) [ARCH_CAPABILITIES, no TSX]
x86 Denverton-v2          Intel Atom Processor (Denverton) [no MPX, no MONITOR]     
x86 Dhyana-v2             Hygon Dhyana Processor [no MONITOR]                       
x86 EPYC-v2               AMD EPYC Processor [IBPB]                                 
x86 EPYC-v3               AMD EPYC Processor [IBPB, no MONITOR]                     
x86 Haswell-v2            Intel Core Processor (Haswell) [no TSX]                   
x86 Haswell-v3            Intel Core Processor (Haswell) [IBRS]                     
x86 Haswell-v4            Intel Core Processor (Haswell) [no TSX, IBRS]             
x86 Icelake-Client-v2     Intel Core Processor (Icelake) [no TSX]                   
x86 Icelake-Server-v2     Intel Xeon Processor (Icelake) [no TSX]                   
x86 IvyBridge-v2          Intel Xeon E3-12xx v2 (Ivy Bridge) [IBRS]                 
x86 Nehalem-v2            Intel Core i7 9xx (Nehalem Class Core i7) [IBRS]          
x86 Opteron_G3-v2         AMD Opteron 23xx (Gen 3 Class Opteron) [no MONITOR]       
x86 SandyBridge-v2        Intel Xeon E312xx (Sandy Bridge) [IBRS]                   
x86 Skylake-Client-v2     Intel Core Processor (Skylake) [IBRS]                     
x86 Skylake-Client-v3     Intel Core Processor (Skylake) [no TSX, IBRS]             
x86 Skylake-Server-v2     Intel Xeon Processor (Skylake) [IBRS]                     
x86 Skylake-Server-v3     Intel Xeon Processor (Skylake) [no TSX, IBRS]             
x86 Snowridge-v2          Intel Atom Processor (SnowRidge) [no MPX]                 
x86 Snowridge-v3          Intel Atom Processor (SnowRidge) [no MPX, no MONITOR]     
x86 Westmere-v2           Westmere E56xx/L56xx/X56xx (Nehalem-C) [IBRS]

Changes in v2:
    - Rebase
    - correct the note of Cascadelake v3 (Xiaoyao)

Tao Xu (4):
  target/i386: Add Denverton-v2 (no MPX) CPU model
  target/i386: Remove monitor from some CPU models
  target/i386: Add new property note to versioned CPU models
  target/i386: Add notes for versioned CPU models

 target/i386/cpu.c | 115 +++++++++++++++++++++++++++++++++-------------
 1 file changed, 84 insertions(+), 31 deletions(-)

-- 
2.20.1

[PATCH v3 1/4] target/i386: Add Denverton-v2 (no MPX) CPU model

[Tao Xu]

Because MPX is being removed from the linux kernel, remove MPX feature
from Denverton.

Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
 target/i386/cpu.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 32efa46852..848c992cd3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3592,6 +3592,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
         .xlevel = 0x80000008,
         .model_id = "Intel Atom Processor (Denverton)",
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "monitor", "off" },
+                    { "mpx", "off" },
+                    { /* end of list */ },
+                },
+            },
+            { /* end of list */ },
+        },
     },
     {
         .name = "Snowridge",
-- 
2.20.1

Re: [PATCH v3 1/4] target/i386: Add Denverton-v2 (no MPX) CPU model

[Eduardo Habkost]

On Wed, Feb 12, 2020 at 04:13:25PM +0800, Tao Xu wrote:
> Because MPX is being removed from the linux kernel, remove MPX feature
> from Denverton.
> 
> Signed-off-by: Tao Xu <tao3.xu@intel.com>

Queued, thanks!

-- 
Eduardo

[PATCH v3 2/4] target/i386: Remove monitor from some CPU models

[Tao Xu]

Add new version of Snowridge, Denverton, Opteron_G3, EPYC, and Dhyana
CPU model to remove MONITOR/MWAIT feature.

After QEMU/KVM use "-overcommit cpu-pm=on" to expose MONITOR/MWAIT
(commit id 6f131f13e68d648a8e4f083c667ab1acd88ce4cd), the MONITOR/MWAIT
feature in these CPU model is unused.

Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
 target/i386/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 848c992cd3..6905e4eabd 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3731,6 +3731,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
                     { /* end of list */ },
                 },
             },
+            {
+                .version = 3,
+                .props = (PropValue[]) {
+                    /* mpx was already removed by -v2 above */
+                    { "monitor", "off" },
+                    { /* end of list */ },
+                },
+            },
             { /* end of list */ },
         },
     },
@@ -3842,6 +3850,17 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
         .xlevel = 0x80000008,
         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "monitor", "off" },
+                    { /* end of list */ },
+                },
+            },
+            { /* end of list */ },
+        },
     },
     {
         .name = "Opteron_G4",
@@ -3966,6 +3985,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
                     { /* end of list */ }
                 }
             },
+            {
+                .version = 3,
+                .props = (PropValue[]) {
+                    /* ibpb was already enabled by -v2 above */
+                    { "monitor", "off" },
+                    { /* end of list */ },
+                },
+            },
             { /* end of list */ }
         }
     },
@@ -4018,6 +4045,17 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .xlevel = 0x8000001E,
         .model_id = "Hygon Dhyana Processor",
         .cache_info = &epyc_cache_info,
+        .versions = (X86CPUVersionDefinition[]) {
+            { .version = 1 },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "monitor", "off" },
+                    { /* end of list */ },
+                },
+            },
+            { /* end of list */ },
+        },
     },
 };
 
-- 
2.20.1

Re: [PATCH v3 2/4] target/i386: Remove monitor from some CPU models

[Eduardo Habkost]

On Wed, Feb 12, 2020 at 04:13:26PM +0800, Tao Xu wrote:
> Add new version of Snowridge, Denverton, Opteron_G3, EPYC, and Dhyana
> CPU model to remove MONITOR/MWAIT feature.
> 
> After QEMU/KVM use "-overcommit cpu-pm=on" to expose MONITOR/MWAIT
> (commit id 6f131f13e68d648a8e4f083c667ab1acd88ce4cd), the MONITOR/MWAIT
> feature in these CPU model is unused.
> 
> Signed-off-by: Tao Xu <tao3.xu@intel.com>

What exactly is the problem you are trying to fix?

No CPU model will ever have monitor=on set by default with KVM,
because kvm_default_props has a monitor=off element.

> ---
>  target/i386/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 848c992cd3..6905e4eabd 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3731,6 +3731,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
>                      { /* end of list */ },
>                  },
>              },
> +            {
> +                .version = 3,
> +                .props = (PropValue[]) {
> +                    /* mpx was already removed by -v2 above */
> +                    { "monitor", "off" },
> +                    { /* end of list */ },
> +                },
> +            },
>              { /* end of list */ },
>          },
>      },
> @@ -3842,6 +3850,17 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
>          .xlevel = 0x80000008,
>          .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
> +        .versions = (X86CPUVersionDefinition[]) {
> +            { .version = 1 },
> +            {
> +                .version = 2,
> +                .props = (PropValue[]) {
> +                    { "monitor", "off" },
> +                    { /* end of list */ },
> +                },
> +            },
> +            { /* end of list */ },
> +        },
>      },
>      {
>          .name = "Opteron_G4",
> @@ -3966,6 +3985,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
>                      { /* end of list */ }
>                  }
>              },
> +            {
> +                .version = 3,
> +                .props = (PropValue[]) {
> +                    /* ibpb was already enabled by -v2 above */
> +                    { "monitor", "off" },
> +                    { /* end of list */ },
> +                },
> +            },
>              { /* end of list */ }
>          }
>      },
> @@ -4018,6 +4045,17 @@ static X86CPUDefinition builtin_x86_defs[] = {
>          .xlevel = 0x8000001E,
>          .model_id = "Hygon Dhyana Processor",
>          .cache_info = &epyc_cache_info,
> +        .versions = (X86CPUVersionDefinition[]) {
> +            { .version = 1 },
> +            {
> +                .version = 2,
> +                .props = (PropValue[]) {
> +                    { "monitor", "off" },
> +                    { /* end of list */ },
> +                },
> +            },
> +            { /* end of list */ },
> +        },
>      },
>  };
>  
> -- 
> 2.20.1
> 
> 

-- 
Eduardo

Re: [PATCH v3 2/4] target/i386: Remove monitor from some CPU models

[Tao Xu]

On 2/29/2020 5:39 AM, Eduardo Habkost wrote:
> On Wed, Feb 12, 2020 at 04:13:26PM +0800, Tao Xu wrote:
>> Add new version of Snowridge, Denverton, Opteron_G3, EPYC, and Dhyana
>> CPU model to uremove MONITOR/MWAIT featre.
>>
>> After QEMU/KVM use "-overcommit cpu-pm=on" to expose MONITOR/MWAIT
>> (commit id 6f131f13e68d648a8e4f083c667ab1acd88ce4cd), the MONITOR/MWAIT
>> feature in these CPU model is unused.
>>
>> Signed-off-by: Tao Xu <tao3.xu@intel.com>
> 
> What exactly is the problem you are trying to fix?
> 
> No CPU model will ever have monitor=on set by default with KVM,
> because kvm_default_props has a monitor=off element.
> 

Maybe it is not a fix. For example, when we boot a guest with Denverton
cpu model, guest cannot detect MONITOR/MWAIT and boot with no warning, 
because of "monitor=off" by default. The MONITOR/MWAIT feature in these 
CPU model is unused,but no harm. I am wondering if we should remove it 
from existing CPU models.

Re: [PATCH v3 2/4] target/i386: Remove monitor from some CPU models

[Eduardo Habkost]

On Mon, Mar 02, 2020 at 07:47:28PM +0800, Tao Xu wrote:
> On 2/29/2020 5:39 AM, Eduardo Habkost wrote:
> > On Wed, Feb 12, 2020 at 04:13:26PM +0800, Tao Xu wrote:
> > > Add new version of Snowridge, Denverton, Opteron_G3, EPYC, and Dhyana
> > > CPU model to uremove MONITOR/MWAIT featre.
> > > 
> > > After QEMU/KVM use "-overcommit cpu-pm=on" to expose MONITOR/MWAIT
> > > (commit id 6f131f13e68d648a8e4f083c667ab1acd88ce4cd), the MONITOR/MWAIT
> > > feature in these CPU model is unused.
> > > 
> > > Signed-off-by: Tao Xu <tao3.xu@intel.com>
> > 
> > What exactly is the problem you are trying to fix?
> > 
> > No CPU model will ever have monitor=on set by default with KVM,
> > because kvm_default_props has a monitor=off element.
> > 
> 
> Maybe it is not a fix. For example, when we boot a guest with Denverton
> cpu model, guest cannot detect MONITOR/MWAIT and boot with no warning,
> because of "monitor=off" by default. The MONITOR/MWAIT feature in these CPU
> model is unused,but no harm. I am wondering if we should remove it from
> existing CPU models.

As monitor=off is on kvm_default_props, changing the CPU model
table will only affect other accelerators (e.g. TCG, where
MONITOR/MWAIT support is advertised as supported).

We shouldn't be dictating policy for other accelerators just
because KVM doesn't support it.  Removing the feature on
kvm_default_props is sufficient.

-- 
Eduardo

Re: [PATCH v3 2/4] target/i386: Remove monitor from some CPU models

[Tao Xu]

On 3/3/2020 1:19 AM, Eduardo Habkost wrote:
> On Mon, Mar 02, 2020 at 07:47:28PM +0800, Tao Xu wrote:
>> On 2/29/2020 5:39 AM, Eduardo Habkost wrote:
>>> On Wed, Feb 12, 2020 at 04:13:26PM +0800, Tao Xu wrote:
>>>> Add new version of Snowridge, Denverton, Opteron_G3, EPYC, and Dhyana
>>>> CPU model to uremove MONITOR/MWAIT featre.
>>>>
>>>> After QEMU/KVM use "-overcommit cpu-pm=on" to expose MONITOR/MWAIT
>>>> (commit id 6f131f13e68d648a8e4f083c667ab1acd88ce4cd), the MONITOR/MWAIT
>>>> feature in these CPU model is unused.
>>>>
>>>> Signed-off-by: Tao Xu <tao3.xu@intel.com>
>>>
>>> What exactly is the problem you are trying to fix?
>>>
>>> No CPU model will ever have monitor=on set by default with KVM,
>>> because kvm_default_props has a monitor=off element.
>>>
>>
>> Maybe it is not a fix. For example, when we boot a guest with Denverton
>> cpu model, guest cannot detect MONITOR/MWAIT and boot with no warning,
>> because of "monitor=off" by default. The MONITOR/MWAIT feature in these CPU
>> model is unused,but no harm. I am wondering if we should remove it from
>> existing CPU models.
> 
> As monitor=off is on kvm_default_props, changing the CPU model
> table will only affect other accelerators (e.g. TCG, where
> MONITOR/MWAIT support is advertised as supported).
> 
> We shouldn't be dictating policy for other accelerators just
> because KVM doesn't support it.  Removing the feature on
> kvm_default_props is sufficient.
> 
I understand, thanks.

[PATCH v3 3/4] target/i386: Add new property note to versioned CPU models

[Tao Xu]

Add additional information for -cpu help to indicate the changes in this
version of CPU model.

Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
 target/i386/cpu.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6905e4eabd..81a039beb6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1690,6 +1690,7 @@ typedef struct PropValue {
 typedef struct X86CPUVersionDefinition {
     X86CPUVersion version;
     const char *alias;
+    const char *note;
     PropValue *props;
 } X86CPUVersionDefinition;
 
@@ -1720,6 +1721,7 @@ struct X86CPUModel {
     X86CPUDefinition *cpudef;
     /* CPU model version */
     X86CPUVersion version;
+    const char *note;
     /*
      * If true, this is an alias CPU model.
      * This matters only for "-cpu help" and query-cpu-definitions
@@ -4899,6 +4901,7 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
     g_autofree char *name = x86_cpu_class_get_model_name(cc);
     g_autofree char *desc = g_strdup(cc->model_description);
     g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
+    g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
 
     if (!desc && alias_of) {
         if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
@@ -4907,11 +4910,14 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
             desc = g_strdup_printf("(alias of %s)", alias_of);
         }
     }
+    if (!desc && cc->model && cc->model->note) {
+        desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
+    }
     if (!desc) {
-        desc = x86_cpu_class_get_model_id(cc);
+        desc = g_strdup_printf("%s", model_id);
     }
 
-    qemu_printf("x86 %-20s  %-48s\n", name, desc);
+    qemu_printf("x86 %-20s  %-58s\n", name, desc);
 }
 
 /* list available CPU models and flags */
@@ -5388,6 +5394,7 @@ static void x86_register_cpudef_types(X86CPUDefinition *def)
             x86_cpu_versioned_model_name(def, vdef->version);
         m->cpudef = def;
         m->version = vdef->version;
+        m->note = vdef->note;
         x86_register_cpu_model_type(name, m);
 
         if (vdef->alias) {
-- 
2.20.1

Re: [PATCH v3 3/4] target/i386: Add new property note to versioned CPU models

[Eduardo Habkost]

On Wed, Feb 12, 2020 at 04:13:27PM +0800, Tao Xu wrote:
> Add additional information for -cpu help to indicate the changes in this
> version of CPU model.
> 
> Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
> Signed-off-by: Tao Xu <tao3.xu@intel.com>

Queued, thanks!

-- 
Eduardo

[PATCH v3 4/4] target/i386: Add notes for versioned CPU models

[Tao Xu]

Add which features are added or removed in this version. Remove the
changed model-id in versioned CPU models, to keep the model name
unchanged at /proc/cpuinfo inside the VM.

Signed-off-by: Tao Xu <tao3.xu@intel.com>
---

Changes in v2:
    - correct the note of Cascadelake v3 (Xiaoyao)
---
 target/i386/cpu.c | 54 ++++++++++++++++++++++-------------------------
 1 file changed, 25 insertions(+), 29 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 81a039beb6..739ef4ce91 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2278,10 +2278,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "Nehalem-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
                     { /* end of list */ }
                 }
             },
@@ -2359,10 +2358,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "Westmere-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Westmere E56xx/L56xx/X56xx (IBRS update)" },
                     { /* end of list */ }
                 }
             },
@@ -2445,10 +2443,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "SandyBridge-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
                     { /* end of list */ }
                 }
             },
@@ -2537,10 +2534,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "IvyBridge-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
                     { /* end of list */ }
                 }
             },
@@ -2634,17 +2630,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "Haswell-noTSX",
+                .note = "no TSX",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
                     { "stepping", "1" },
-                    { "model-id", "Intel Core Processor (Haswell, no TSX)", },
                     { /* end of list */ }
                 },
             },
             {
                 .version = 3,
                 .alias = "Haswell-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     /* Restore TSX features removed by -v2 above */
                     { "hle", "on" },
@@ -2655,21 +2652,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
                      */
                     { "stepping", "4" },
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Core Processor (Haswell, IBRS)" },
                     { /* end of list */ }
                 }
             },
             {
                 .version = 4,
                 .alias = "Haswell-noTSX-IBRS",
+                .note = "no TSX, IBRS",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
                     /* spec-ctrl was already enabled by -v3 above */
                     { "stepping", "1" },
-                    { "model-id",
-                      "Intel Core Processor (Haswell, no TSX, IBRS)" },
                     { /* end of list */ }
                 }
             },
@@ -2765,35 +2759,33 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "Broadwell-noTSX",
+                .note = "no TSX",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
-                    { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
                     { /* end of list */ }
                 },
             },
             {
                 .version = 3,
                 .alias = "Broadwell-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     /* Restore TSX features removed by -v2 above */
                     { "hle", "on" },
                     { "rtm", "on" },
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Core Processor (Broadwell, IBRS)" },
                     { /* end of list */ }
                 }
             },
             {
                 .version = 4,
                 .alias = "Broadwell-noTSX-IBRS",
+                .note = "no TSX, IBRS",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
                     /* spec-ctrl was already enabled by -v3 above */
-                    { "model-id",
-                      "Intel Core Processor (Broadwell, no TSX, IBRS)" },
                     { /* end of list */ }
                 }
             },
@@ -2893,22 +2885,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "IBRS",
                 .alias = "Skylake-Client-IBRS",
                 .props = (PropValue[]) {
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Core Processor (Skylake, IBRS)" },
                     { /* end of list */ }
                 }
             },
             {
                 .version = 3,
                 .alias = "Skylake-Client-noTSX-IBRS",
+                .note = "no TSX, IBRS",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
-                    { "model-id",
-                      "Intel Core Processor (Skylake, IBRS, no TSX)" },
                     { /* end of list */ }
                 }
             },
@@ -3016,24 +3006,22 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "Skylake-Server-IBRS",
+                .note = "IBRS",
                 .props = (PropValue[]) {
                     /* clflushopt was not added to Skylake-Server-IBRS */
                     /* TODO: add -v3 including clflushopt */
                     { "clflushopt", "off" },
                     { "spec-ctrl", "on" },
-                    { "model-id",
-                      "Intel Xeon Processor (Skylake, IBRS)" },
                     { /* end of list */ }
                 }
             },
             {
                 .version = 3,
                 .alias = "Skylake-Server-noTSX-IBRS",
+                .note = "no TSX, IBRS",
                 .props = (PropValue[]) {
                     { "hle", "off" },
                     { "rtm", "off" },
-                    { "model-id",
-                      "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
                     { /* end of list */ }
                 }
             },
@@ -3142,6 +3130,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .versions = (X86CPUVersionDefinition[]) {
             { .version = 1 },
             { .version = 2,
+              .note = "ARCH_CAPABILITIES",
               .props = (PropValue[]) {
                   { "arch-capabilities", "on" },
                   { "rdctl-no", "on" },
@@ -3153,6 +3142,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             },
             { .version = 3,
               .alias = "Cascadelake-Server-noTSX",
+              .note = "ARCH_CAPABILITIES, no TSX",
               .props = (PropValue[]) {
                   { "hle", "off" },
                   { "rtm", "off" },
@@ -3374,6 +3364,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no TSX",
                 .alias = "Icelake-Client-noTSX",
                 .props = (PropValue[]) {
                     { "hle", "off" },
@@ -3491,6 +3482,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no TSX",
                 .alias = "Icelake-Server-noTSX",
                 .props = (PropValue[]) {
                     { "hle", "off" },
@@ -3598,6 +3590,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no MPX, no MONITOR",
                 .props = (PropValue[]) {
                     { "monitor", "off" },
                     { "mpx", "off" },
@@ -3727,14 +3720,15 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no MPX",
                 .props = (PropValue[]) {
                     { "mpx", "off" },
-                    { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
                     { /* end of list */ },
                 },
             },
             {
                 .version = 3,
+                .note = "no MPX, no MONITOR",
                 .props = (PropValue[]) {
                     /* mpx was already removed by -v2 above */
                     { "monitor", "off" },
@@ -3856,6 +3850,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no MONITOR",
                 .props = (PropValue[]) {
                     { "monitor", "off" },
                     { /* end of list */ },
@@ -3980,15 +3975,15 @@ static X86CPUDefinition builtin_x86_defs[] = {
             {
                 .version = 2,
                 .alias = "EPYC-IBPB",
+                .note = "IBPB",
                 .props = (PropValue[]) {
                     { "ibpb", "on" },
-                    { "model-id",
-                      "AMD EPYC Processor (with IBPB)" },
                     { /* end of list */ }
                 }
             },
             {
                 .version = 3,
+                .note = "IBPB, no MONITOR",
                 .props = (PropValue[]) {
                     /* ibpb was already enabled by -v2 above */
                     { "monitor", "off" },
@@ -4051,6 +4046,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
             { .version = 1 },
             {
                 .version = 2,
+                .note = "no MONITOR",
                 .props = (PropValue[]) {
                     { "monitor", "off" },
                     { /* end of list */ },
-- 
2.20.1

Re: [PATCH v3 4/4] target/i386: Add notes for versioned CPU models

[Igor Mammedov]

On Wed, 12 Feb 2020 16:13:28 +0800
Tao Xu <tao3.xu@intel.com> wrote:

> Add which features are added or removed in this version. Remove the
> changed model-id in versioned CPU models, to keep the model name
> unchanged at /proc/cpuinfo inside the VM.
> 
> Signed-off-by: Tao Xu <tao3.xu@intel.com>
> ---
> 
> Changes in v2:
>     - correct the note of Cascadelake v3 (Xiaoyao)
> ---
>  target/i386/cpu.c | 54 ++++++++++++++++++++++-------------------------
>  1 file changed, 25 insertions(+), 29 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 81a039beb6..739ef4ce91 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -2278,10 +2278,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              {
>                  .version = 2,
>                  .alias = "Nehalem-IBRS",
> +                .note = "IBRS",
>                  .props = (PropValue[]) {
>                      { "spec-ctrl", "on" },
> -                    { "model-id",
> -                      "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
>                      { /* end of list */ }
>                  }
>              },
> @@ -2359,10 +2358,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              {
>                  .version = 2,
>                  .alias = "Westmere-IBRS",
> +                .note = "IBRS",
>                  .props = (PropValue[]) {
>                      { "spec-ctrl", "on" },
> -                    { "model-id",
> -                      "Westmere E56xx/L56xx/X56xx (IBRS update)" },
>                      { /* end of list */ }
>                  }
>              },
> @@ -2445,10 +2443,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              {
>                  .version = 2,
>                  .alias = "SandyBridge-IBRS",
> +                .note = "IBRS",
>                  .props = (PropValue[]) {
>                      { "spec-ctrl", "on" },
> -                    { "model-id",
> -                      "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
>                      { /* end of list */ }
>                  }
>              },
> @@ -2537,10 +2534,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              {
>                  .version = 2,
>                  .alias = "IvyBridge-IBRS",
> +                .note = "IBRS",
>                  .props = (PropValue[]) {
>                      { "spec-ctrl", "on" },
> -                    { "model-id",
> -                      "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
>                      { /* end of list */ }
>                  }
>              },
> @@ -2634,17 +2630,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              {
>                  .version = 2,
>                  .alias = "Haswell-noTSX",
> +                .note = "no TSX",
>                  .props = (PropValue[]) {
>                      { "hle", "off" },
>                      { "rtm", "off" },
>                      { "stepping", "1" },
> -                    { "model-id", "Intel Core Processor (Haswell, no TSX)", },
>                      { /* end of list */ }
>                  },
>              },
>              {
>                  .version = 3,
>                  .alias = "Haswell-IBRS",
> +                .note = "IBRS",
>                  .props = (PropValue[]) {
>                      /* Restore TSX features removed by -v2 above */
>                      { "hle", "on" },
> @@ -2655,21 +2652,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
>                       */
>                      { "stepping", "4" },
>                      { "spec-ctrl", "on" },
> -                    { "model-id",
> -                      "Intel Core Processor (Haswell, IBRS)" },
>                      { /* end of list */ }
>                  }
>              },
>              {
>                  .version = 4,
>                  .alias = "Haswell-noTSX-IBRS",
> +                .note = "no TSX, IBRS",
>                  .props = (PropValue[]) {
>                      { "hle", "off" },
>                      { "rtm", "off" },
>                      /* spec-ctrl was already enabled by -v3 above */
>                      { "stepping", "1" },
> -                    { "model-id",
> -                      "Intel Core Processor (Haswell, no TSX, IBRS)" },
>                      { /* end of list */ }
>                  }
>              },
> @@ -2765,35 +2759,33 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              {
>                  .version = 2,
>                  .alias = "Broadwell-noTSX",
> +                .note = "no TSX",
>                  .props = (PropValue[]) {
>                      { "hle", "off" },
>                      { "rtm", "off" },
> -                    { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
>                      { /* end of list */ }
>                  },
>              },
>              {
>                  .version = 3,
>                  .alias = "Broadwell-IBRS",
> +                .note = "IBRS",
>                  .props = (PropValue[]) {
>                      /* Restore TSX features removed by -v2 above */
>                      { "hle", "on" },
>                      { "rtm", "on" },
>                      { "spec-ctrl", "on" },
> -                    { "model-id",
> -                      "Intel Core Processor (Broadwell, IBRS)" },
>                      { /* end of list */ }
>                  }
>              },
>              {
>                  .version = 4,
>                  .alias = "Broadwell-noTSX-IBRS",
> +                .note = "no TSX, IBRS",
>                  .props = (PropValue[]) {
>                      { "hle", "off" },
>                      { "rtm", "off" },
>                      /* spec-ctrl was already enabled by -v3 above */
> -                    { "model-id",
> -                      "Intel Core Processor (Broadwell, no TSX, IBRS)" },
>                      { /* end of list */ }
>                  }
>              },
> @@ -2893,22 +2885,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              { .version = 1 },
>              {
>                  .version = 2,
> +                .note = "IBRS",
>                  .alias = "Skylake-Client-IBRS",
>                  .props = (PropValue[]) {
>                      { "spec-ctrl", "on" },
> -                    { "model-id",
> -                      "Intel Core Processor (Skylake, IBRS)" },
>                      { /* end of list */ }
>                  }
>              },
>              {
>                  .version = 3,
>                  .alias = "Skylake-Client-noTSX-IBRS",
> +                .note = "no TSX, IBRS",
>                  .props = (PropValue[]) {
>                      { "hle", "off" },
>                      { "rtm", "off" },
> -                    { "model-id",
> -                      "Intel Core Processor (Skylake, IBRS, no TSX)" },
>                      { /* end of list */ }
>                  }
>              },
> @@ -3016,24 +3006,22 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              {
>                  .version = 2,
>                  .alias = "Skylake-Server-IBRS",
> +                .note = "IBRS",
>                  .props = (PropValue[]) {
>                      /* clflushopt was not added to Skylake-Server-IBRS */
>                      /* TODO: add -v3 including clflushopt */
>                      { "clflushopt", "off" },
>                      { "spec-ctrl", "on" },
> -                    { "model-id",
> -                      "Intel Xeon Processor (Skylake, IBRS)" },
>                      { /* end of list */ }
>                  }
>              },
>              {
>                  .version = 3,
>                  .alias = "Skylake-Server-noTSX-IBRS",
> +                .note = "no TSX, IBRS",
>                  .props = (PropValue[]) {
>                      { "hle", "off" },
>                      { "rtm", "off" },
> -                    { "model-id",
> -                      "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
>                      { /* end of list */ }
>                  }
>              },
> @@ -3142,6 +3130,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>          .versions = (X86CPUVersionDefinition[]) {
>              { .version = 1 },
>              { .version = 2,
> +              .note = "ARCH_CAPABILITIES",

what's ARCH_CAPABILITIES?

>                .props = (PropValue[]) {
>                    { "arch-capabilities", "on" },
>                    { "rdctl-no", "on" },
> @@ -3153,6 +3142,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              },
>              { .version = 3,
>                .alias = "Cascadelake-Server-noTSX",
> +              .note = "ARCH_CAPABILITIES, no TSX",
>                .props = (PropValue[]) {
>                    { "hle", "off" },
>                    { "rtm", "off" },
> @@ -3374,6 +3364,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              { .version = 1 },
>              {
>                  .version = 2,
> +                .note = "no TSX",
>                  .alias = "Icelake-Client-noTSX",
>                  .props = (PropValue[]) {
>                      { "hle", "off" },
> @@ -3491,6 +3482,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              { .version = 1 },
>              {
>                  .version = 2,
> +                .note = "no TSX",
>                  .alias = "Icelake-Server-noTSX",
>                  .props = (PropValue[]) {
>                      { "hle", "off" },
> @@ -3598,6 +3590,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              { .version = 1 },
>              {
>                  .version = 2,
> +                .note = "no MPX, no MONITOR",
>                  .props = (PropValue[]) {
>                      { "monitor", "off" },
>                      { "mpx", "off" },
> @@ -3727,14 +3720,15 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              { .version = 1 },
>              {
>                  .version = 2,
> +                .note = "no MPX",
>                  .props = (PropValue[]) {
>                      { "mpx", "off" },
> -                    { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
>                      { /* end of list */ },
>                  },
>              },
>              {
>                  .version = 3,
> +                .note = "no MPX, no MONITOR",
>                  .props = (PropValue[]) {
>                      /* mpx was already removed by -v2 above */
>                      { "monitor", "off" },
> @@ -3856,6 +3850,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              { .version = 1 },
>              {
>                  .version = 2,
> +                .note = "no MONITOR",
>                  .props = (PropValue[]) {
>                      { "monitor", "off" },
>                      { /* end of list */ },
> @@ -3980,15 +3975,15 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              {
>                  .version = 2,
>                  .alias = "EPYC-IBPB",
> +                .note = "IBPB",
>                  .props = (PropValue[]) {
>                      { "ibpb", "on" },
> -                    { "model-id",
> -                      "AMD EPYC Processor (with IBPB)" },
>                      { /* end of list */ }
>                  }
>              },
>              {
>                  .version = 3,
> +                .note = "IBPB, no MONITOR",
>                  .props = (PropValue[]) {
>                      /* ibpb was already enabled by -v2 above */
>                      { "monitor", "off" },
> @@ -4051,6 +4046,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              { .version = 1 },
>              {
>                  .version = 2,
> +                .note = "no MONITOR",
>                  .props = (PropValue[]) {
>                      { "monitor", "off" },
>                      { /* end of list */ },

Re: [PATCH v3 4/4] target/i386: Add notes for versioned CPU models

[Tao Xu]

On 2/12/2020 5:00 PM, Igor Mammedov wrote:
> On Wed, 12 Feb 2020 16:13:28 +0800
> Tao Xu <tao3.xu@intel.com> wrote:
> 
>> Add which features are added or removed in this version. Remove the
>> changed model-id in versioned CPU models, to keep the model name
>> unchanged at /proc/cpuinfo inside the VM.
>>
>> Signed-off-by: Tao Xu <tao3.xu@intel.com>
>> ---
>>
>> Changes in v2:
>>      - correct the note of Cascadelake v3 (Xiaoyao)
>> ---
>>   target/i386/cpu.c | 54 ++++++++++++++++++++++-------------------------
>>   1 file changed, 25 insertions(+), 29 deletions(-)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 81a039beb6..739ef4ce91 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
[...]
>> @@ -3142,6 +3130,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>>           .versions = (X86CPUVersionDefinition[]) {
>>               { .version = 1 },
>>               { .version = 2,
>> +              .note = "ARCH_CAPABILITIES",
> 
> what's ARCH_CAPABILITIES?
> 

These are some features exposed by MSR_IA32_ARCH_CAPABILITIES. For 
Cascadelake, these are "rdctl-no" "ibrs-all" "skip-l1dfl-vmentry" "mds-no"

Re: [PATCH v3 4/4] target/i386: Add notes for versioned CPU models

[Eduardo Habkost]

On Wed, Feb 12, 2020 at 04:13:28PM +0800, Tao Xu wrote:
> Add which features are added or removed in this version. Remove the
> changed model-id in versioned CPU models, to keep the model name
> unchanged at /proc/cpuinfo inside the VM.
> 
> Signed-off-by: Tao Xu <tao3.xu@intel.com>
> ---
> 
> Changes in v2:
>     - correct the note of Cascadelake v3 (Xiaoyao)
> ---
>  target/i386/cpu.c | 54 ++++++++++++++++++++++-------------------------
>  1 file changed, 25 insertions(+), 29 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 81a039beb6..739ef4ce91 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -2278,10 +2278,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              {
>                  .version = 2,
>                  .alias = "Nehalem-IBRS",
> +                .note = "IBRS",
>                  .props = (PropValue[]) {
>                      { "spec-ctrl", "on" },
> -                    { "model-id",
> -                      "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
>                      { /* end of list */ }

Changing model-id is guest-visible, so we can't do this.  The
same applies to the other models where model-id is being removed.

I suggest using the .note property only on the CPU model versions
that don't have custom model-id set yet, or when existing
information on model-id is incomplete.

For future CPU model versions, we can start using only .note and
stop changing model-id.

-- 
Eduardo

Re: [PATCH v3 4/4] target/i386: Add notes for versioned CPU models

[Tao Xu]

On 2/29/2020 5:52 AM, Eduardo Habkost wrote:
> On Wed, Feb 12, 2020 at 04:13:28PM +0800, Tao Xu wrote:
>> Add which features are added or removed in this version. Remove the
>> changed model-id in versioned CPU models, to keep the model name
>> unchanged at /proc/cpuinfo inside the VM.
>>
>> Signed-off-by: Tao Xu <tao3.xu@intel.com>
>> ---
>>
>> Changes in v2:
>>      - correct the note of Cascadelake v3 (Xiaoyao)
>> ---
>>   target/i386/cpu.c | 54 ++++++++++++++++++++++-------------------------
>>   1 file changed, 25 insertions(+), 29 deletions(-)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 81a039beb6..739ef4ce91 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -2278,10 +2278,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
>>               {
>>                   .version = 2,
>>                   .alias = "Nehalem-IBRS",
>> +                .note = "IBRS",
>>                   .props = (PropValue[]) {
>>                       { "spec-ctrl", "on" },
>> -                    { "model-id",
>> -                      "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
>>                       { /* end of list */ }
> 
> Changing model-id is guest-visible, so we can't do this.  The
> same applies to the other models where model-id is being removed.
> 
> I suggest using the .note property only on the CPU model versions
> that don't have custom model-id set yet, or when existing
> information on model-id is incomplete.
> 
> For future CPU model versions, we can start using only .note and
> stop changing model-id.
> 

Got it,thanks!