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[79.176.28.95]) by smtp.gmail.com with ESMTPSA id y27sm1300746qta.50.2020.02.13.02.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2020 02:17:18 -0800 (PST) Date: Thu, 13 Feb 2020 05:17:14 -0500 From: "Michael S. Tsirkin" To: Yubo Miao Subject: Re: [RFC 2/2] pci-expender-bus:Add pcie-root-port to pxb-pcie under arm. Message-ID: <20200213051310-mutt-send-email-mst@kernel.org> References: <20200213074952.544-1-miaoyubo@huawei.com> <20200213074952.544-3-miaoyubo@huawei.com> MIME-Version: 1.0 In-Reply-To: <20200213074952.544-3-miaoyubo@huawei.com> X-MC-Unique: YsVjjW1cNWuwAhP4zi1I8g-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: quoted-printable Content-Disposition: inline X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, imammedo@redhat.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, shannon.zhaosl@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Feb 13, 2020 at 03:49:52PM +0800, Yubo Miao wrote: > From: miaoyubo >=20 > Since devices could not directly plugged into pxb-pcie, Hmm is this different from the root port? intergrated devices do exist for that actually. > under arm, how is arm special? > one > pcie-root port is plugged into pxb-pcie. Due to the bus for each pxb-pcie > is defined as 2 in acpi dsdt tables(one for pxb-pcie, one for pcie-root-p= ort), > only one device could be plugged into one pxb-pcie. So why can't we have users specify any number of root ports using -device? then make acpi tables match the # of ports created? >=20 > Signed-off-by: miaoyubo > --- > hw/pci-bridge/pci_expander_bridge.c | 9 +++++++++ > include/hw/pci/pcie_port.h | 1 + > 2 files changed, 10 insertions(+) >=20 > diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expa= nder_bridge.c > index 47aaaf8fd1..3d896dd452 100644 > --- a/hw/pci-bridge/pci_expander_bridge.c > +++ b/hw/pci-bridge/pci_expander_bridge.c > @@ -15,6 +15,7 @@ > #include "hw/pci/pci.h" > #include "hw/pci/pci_bus.h" > #include "hw/pci/pci_host.h" > +#include "hw/pci/pcie_port.h" > #include "hw/qdev-properties.h" > #include "hw/pci/pci_bridge.h" > #include "qemu/range.h" > @@ -233,7 +234,15 @@ static void pxb_dev_realize_common(PCIDevice *dev, b= ool pcie, Error **errp) > =20 > ds =3D qdev_create(NULL, TYPE_PXB_HOST); > if (pcie) { > +#ifdef __aarch64__ > + bus =3D pci_root_bus_new(ds, "pxb-pcie-internal", > + NULL, NULL, 0, TYPE_PXB_PCIE_BUS); > + bds =3D qdev_create(BUS(bus), "pcie-root-port"); > + bds->id =3D dev_name; > + qdev_prop_set_uint8(bds, PCIE_ROOT_PORT_PROP_CHASSIS, pxb->bus_n= r); > +#else > bus =3D pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_P= CIE_BUS); > +#endif What does all this have to do with building on aarch64? > } else { > bus =3D pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE= _PXB_BUS); > bds =3D qdev_create(BUS(bus), "pci-bridge"); > diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h > index 4b3d254b08..b41d473220 100644 > --- a/include/hw/pci/pcie_port.h > +++ b/include/hw/pci/pcie_port.h > @@ -64,6 +64,7 @@ int pcie_chassis_add_slot(struct PCIESlot *slot); > void pcie_chassis_del_slot(PCIESlot *s); > =20 > #define TYPE_PCIE_ROOT_PORT "pcie-root-port-base" > +#define PCIE_ROOT_PORT_PROP_CHASSIS "chassis" If you are going to do this, replace other instances of "chassis" with the macro. > #define PCIE_ROOT_PORT_CLASS(klass) \ > OBJECT_CLASS_CHECK(PCIERootPortClass, (klass), TYPE_PCIE_ROOT_PORT) > #define PCIE_ROOT_PORT_GET_CLASS(obj) \ > --=20 > 2.19.1 >=20