From: David Gibson <david@gibson.dropbear.id.au>
To: Fabiano Rosas <farosas@linux.ibm.com>
Cc: lvivier@redhat.com, groug@kaod.org, qemu-devel@nongnu.org,
paulus@samba.org, clg@kaod.org, qemu-ppc@nongnu.org,
philmd@redhat.com
Subject: Re: [PATCH v3 11/12] target/ppc: Streamline construction of VRMA SLB entry
Date: Thu, 20 Feb 2020 14:13:26 +1100 [thread overview]
Message-ID: <20200220031326.GN1764@umbus.fritz.box> (raw)
In-Reply-To: <875zg2d4sx.fsf@linux.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 2185 bytes --]
On Wed, Feb 19, 2020 at 11:34:22AM -0300, Fabiano Rosas wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
>
> Hi, just a nitpick, feel free to ignore.
>
> > When in VRMA mode (i.e. a guest thinks it has the MMU off, but the
> > hypervisor is still applying translation) we use a special SLB entry,
> > rather than looking up an SLBE by address as we do when guest translation
> > is on.
> >
> > We build that special entry in ppc_hash64_update_vrma() along with some
> > logic for handling some non-VRMA cases. Split the actual build of the
> > VRMA SLBE into a separate helper and streamline it a bit.
> >
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > ---
> > target/ppc/mmu-hash64.c | 79 ++++++++++++++++++++---------------------
> > 1 file changed, 38 insertions(+), 41 deletions(-)
> >
> > diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> > index 170a78bd2e..06cfff9860 100644
> > --- a/target/ppc/mmu-hash64.c
> > +++ b/target/ppc/mmu-hash64.c
> > @@ -789,6 +789,39 @@ static target_ulong rmls_limit(PowerPCCPU *cpu)
> > }
> > }
> >
> > +static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
> > +{
> > + CPUPPCState *env = &cpu->env;
> > + target_ulong lpcr = env->spr[SPR_LPCR];
> > + uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
> > + target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MASK);
> > + int i;
> > +
> > + /*
> > + * Make one up. Mostly ignore the ESID which will not be needed
> > + * for translation
> > + */
>
> I find this comment a bit vague. I suggest we either leave it behind or
> make it more precise. The ISA says:
>
> "translation of effective addresses to virtual addresses use the SLBE
> values in Figure 18 instead of the entry in the SLB corresponding to the
> ESID"
Yeah, it wasn't very helpful in its initial location, and it's even
less helpful here. I've dropped it.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
next prev parent reply other threads:[~2020-02-20 3:24 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-19 0:54 [PATCH v3 00/12] target/ppc: Correct some errors with real mode handling David Gibson
2020-02-19 0:54 ` [PATCH v3 01/12] ppc: Remove stub support for 32-bit hypervisor mode David Gibson
2020-02-19 14:15 ` Fabiano Rosas
2020-02-19 0:54 ` [PATCH v3 02/12] ppc: Remove stub of PPC970 HID4 implementation David Gibson
2020-02-19 11:18 ` BALATON Zoltan
2020-02-20 0:36 ` David Gibson
2020-02-19 0:54 ` [PATCH v3 03/12] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU David Gibson
2020-02-19 0:54 ` [PATCH v3 04/12] target/ppc: Introduce ppc_hash64_use_vrma() helper David Gibson
2020-02-19 14:06 ` Fabiano Rosas
2020-02-20 2:41 ` Paul Mackerras
2020-02-20 3:10 ` David Gibson
2020-02-19 0:54 ` [PATCH v3 05/12] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 David Gibson
2020-02-19 0:54 ` [PATCH v3 06/12] target/ppc: Remove RMOR register from POWER9 & POWER10 David Gibson
2020-02-19 0:54 ` [PATCH v3 07/12] target/ppc: Use class fields to simplify LPCR masking David Gibson
2020-02-19 0:54 ` [PATCH v3 08/12] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] David Gibson
2020-02-19 0:54 ` [PATCH v3 09/12] target/ppc: Correct RMLS table David Gibson
2020-02-19 0:54 ` [PATCH v3 10/12] target/ppc: Only calculate RMLS derived RMA limit on demand David Gibson
2020-02-19 0:54 ` [PATCH v3 11/12] target/ppc: Streamline construction of VRMA SLB entry David Gibson
2020-02-19 14:34 ` Fabiano Rosas
2020-02-20 3:13 ` David Gibson [this message]
2020-02-19 0:54 ` [PATCH v3 12/12] target/ppc: Don't store VRMA SLBE persistently David Gibson
2020-02-19 1:21 ` [PATCH v3 00/12] target/ppc: Correct some errors with real mode handling no-reply
2020-02-19 2:11 ` David Gibson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200220031326.GN1764@umbus.fritz.box \
--to=david@gibson.dropbear.id.au \
--cc=clg@kaod.org \
--cc=farosas@linux.ibm.com \
--cc=groug@kaod.org \
--cc=lvivier@redhat.com \
--cc=paulus@samba.org \
--cc=philmd@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).