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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/52] target/arm: Provide ARMv8.4-PMU in '-cpu max' Date: Fri, 21 Feb 2020 13:07:16 +0000 Message-Id: <20200221130740.7583-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Set the ID register bits to provide ARMv8.4-PMU (and implicitly also ARMv8.1-PMU) in the 'max' CPU. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-16-peter.maydell@linaro.org --- target/arm/cpu64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f8f74a7ecda..c9452894035 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -703,6 +703,14 @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->id_mmfr3 = u; + u = cpu->isar.id_aa64dfr0; + u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + cpu->isar.id_aa64dfr0 = u; + + u = cpu->isar.id_dfr0; + u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 = u; + /* * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, * so do not set MVFR1.FPHP. Strictly speaking this is not legal, -- 2.20.1