From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0
Date: Mon, 24 Feb 2020 17:28:44 +0000 [thread overview]
Message-ID: <20200224172846.13053-2-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200224172846.13053-1-peter.maydell@linaro.org>
We missed an instance of using FIELD_EX32 on a 64-bit ID
register, in isar_feature_aa64_pmu_8_4(). Fix it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 65171cb30ee..b647d8df916 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3723,8 +3723,8 @@ static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
- FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
+ return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
+ FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
}
/*
--
2.20.1
next prev parent reply other threads:[~2020-02-24 17:29 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-24 17:28 [PATCH 0/3] target/arm: Implement v8.3-RCPC and v8.4-RCPC Peter Maydell
2020-02-24 17:28 ` Peter Maydell [this message]
2020-02-24 17:48 ` [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Philippe Mathieu-Daudé
2020-02-24 18:23 ` Richard Henderson
2020-02-24 17:28 ` [PATCH 2/3] target/arm: Implement v8.3-RCPC Peter Maydell
2020-02-24 18:31 ` Richard Henderson
2020-02-24 17:28 ` [PATCH 3/3] target/arm: Implement v8.4-RCPC Peter Maydell
2020-02-24 18:39 ` Richard Henderson
2020-02-24 18:42 ` Peter Maydell
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