[PATCH v2 02/17] target/arm: Rename isar_feature_aa32_fpdp_v2

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: [PATCH v2 02/17] target/arm: Rename isar_feature_aa32_fpdp_v2
Date: Mon, 24 Feb 2020 14:22:17 -0800	[thread overview]
Message-ID: <20200224222232.13807-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org>

The old name, isar_feature_aa32_fpdp, does not reflect
that the test includes VFPv2.  We will introduce another
feature tests for VFPv3.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h               |  4 ++--
 target/arm/translate-vfp.inc.c | 40 +++++++++++++++++-----------------
 2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a128d48d40..1e6eac0cd2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3470,9 +3470,9 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
     return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
 }
 
-static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
+static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
 {
-    /* Return true if CPU supports double precision floating point */
+    /* Return true if CPU supports double precision floating point, VFPv2 */
     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
 }
 
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index ba46e2557a..e94876c30c 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
         return false;
     }
 
-    if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+    if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
         return false;
     }
 
-    if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+    if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
         return false;
     }
 
-    if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+    if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
         return false;
     }
 
-    if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+    if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -1827,7 +1827,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -1926,7 +1926,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2070,7 +2070,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2143,7 +2143,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2209,7 +2209,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2269,7 +2269,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2330,7 +2330,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2389,7 +2389,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2417,7 +2417,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2445,7 +2445,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2499,7 +2499,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2539,7 +2539,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2632,7 +2632,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
@@ -2728,7 +2728,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
         return false;
     }
 
-    if (!dc_isar_feature(aa32_fpdp, s)) {
+    if (!dc_isar_feature(aa32_fpdp_v2, s)) {
         return false;
     }
 
-- 
2.20.1

next prev parent reply	other threads:[~2020-02-24 22:23 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-24 22:22 [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Richard Henderson
2020-02-24 22:22 ` [PATCH v2 01/17] target/arm: Add isar_feature_aa32_vfp_simd Richard Henderson
2020-02-25 13:18   ` Peter Maydell
2020-02-24 22:22 ` Richard Henderson [this message]
2020-02-24 22:22 ` [PATCH v2 03/17] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Richard Henderson
2020-02-24 22:22 ` [PATCH v2 04/17] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Richard Henderson
2020-02-25 13:20   ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 05/17] target/arm: Improve ID_AA64PFR0 FP/SIMD validation Richard Henderson
2020-02-25 13:24   ` Peter Maydell
2020-02-25 15:55     ` Richard Henderson
2020-02-25 15:58       ` Peter Maydell
2020-02-25 16:00         ` Richard Henderson
2020-02-24 22:22 ` [PATCH v2 06/17] target/arm: Perform fpdp_v2 check first Richard Henderson
2020-02-24 22:22 ` [PATCH v2 07/17] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Richard Henderson
2020-02-24 22:22 ` [PATCH v2 08/17] target/arm: Add missing checks for fpsp_v2 Richard Henderson
2020-02-24 22:22 ` [PATCH v2 09/17] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Richard Henderson
2020-02-25 13:25   ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 10/17] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Richard Henderson
2020-02-24 22:22 ` [PATCH v2 11/17] target/arm: Move VLLDM and VLSTM to vfp.decode Richard Henderson
2020-02-25 13:26   ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 12/17] target/arm: Move the vfp decodetree calls next to the base isa Richard Henderson
2020-02-25 13:29   ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 13/17] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Richard Henderson
2020-02-25 13:30   ` Peter Maydell
2020-02-24 22:22 ` [PATCH v2 14/17] target/arm: Remove ARM_FEATURE_VFP* Richard Henderson
2020-02-24 22:22 ` [PATCH v2 15/17] target/arm: Add formats for some vfp 2 and 3-register insns Richard Henderson
2020-02-24 22:22 ` [PATCH v2 16/17] target/arm: Split VFM decode Richard Henderson
2020-02-24 22:22 ` [PATCH v2 17/17] target/arm: Split VMINMAXNM decode Richard Henderson
2020-02-25 17:40 ` [PATCH v2 00/17] target/arm: vfp feature and decodetree cleanup Peter Maydell

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