[PATCH 0/3] Fix Skylake, Cascadelake and Icelake Server CPU models

[PATCH 0/3] Fix Skylake, Cascadelake and Icelake Server CPU models

[Chenyi Qiang]

Current Skylake-Server, Cascadelake-Server and Icelake-Server CPU models
lack several VMX features. Icelake-Server also lacks two features in
FEAT_7_0_EBX. In addition, The model numbers of Icelake-Client and
Icelake-Server need to be fixed.

Chenyi Qiang (3):
  target/i386: add missing vmx features for several CPU models
  target/i386: add two missing features for Icelake-Server CPU model
  target/i386: modify Icelake-Client and Icelake-Server CPU model number

 target/i386/cpu.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

-- 
2.17.1

[PATCH 1/3] target/i386: add missing vmx features for several CPU models

[Chenyi Qiang]

Add some missing VMX features in Skylake-Server, Cascadelake-Server and
Icelake-Server CPU models based on the output of Paolo's script.

Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
 target/i386/cpu.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 92fafa2659..4e105029ca 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3007,6 +3007,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
         .xlevel = 0x80000008,
         .model_id = "Intel Xeon Processor (Skylake)",
         .versions = (X86CPUVersionDefinition[]) {
@@ -3135,6 +3136,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
         .xlevel = 0x80000008,
         .model_id = "Intel Xeon Processor (Cascadelake)",
         .versions = (X86CPUVersionDefinition[]) {
@@ -3482,7 +3484,9 @@ static X86CPUDefinition builtin_x86_defs[] = {
              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
-             VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
+             VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
+             VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
         .xlevel = 0x80000008,
         .model_id = "Intel Xeon Processor (Icelake)",
         .versions = (X86CPUVersionDefinition[]) {
-- 
2.17.1

[PATCH 2/3] target/i386: add two missing features for Icelake-Server CPU model

[Chenyi Qiang]

Add the SHA_NI and AVX512IFMA feature bits in FEAT_7_0_EBX.

Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
 target/i386/cpu.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 4e105029ca..c0be0f83b4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3419,7 +3419,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
             CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
             CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
-            CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
+            CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT |
+            CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_AVX512IFMA,
         .features[FEAT_7_0_ECX] =
             CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
             CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
-- 
2.17.1

[PATCH 3/3] target/i386: modify Icelake-Client and Icelake-Server CPU model number

[Chenyi Qiang]

According to the Intel Icelake family list, Icelake-Client uses model
number 126(0x7D) and Icelake-Server uses model number 106(0x6A).

Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
 target/i386/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c0be0f83b4..b43a479528 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3276,7 +3276,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .level = 0xd,
         .vendor = CPUID_VENDOR_INTEL,
         .family = 6,
-        .model = 126,
+        .model = 125,
         .stepping = 0,
         .features[FEAT_1_EDX] =
             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
@@ -3389,7 +3389,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .level = 0xd,
         .vendor = CPUID_VENDOR_INTEL,
         .family = 6,
-        .model = 134,
+        .model = 106,
         .stepping = 0,
         .features[FEAT_1_EDX] =
             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
-- 
2.17.1

Re: [PATCH 3/3] target/i386: modify Icelake-Client and Icelake-Server CPU model number

[Jack Wang]

Chenyi Qiang <chenyi.qiang@intel.com> 于2020年2月27日周四 上午10:07写道：
>
> According to the Intel Icelake family list, Icelake-Client uses model
> number 126(0x7D)
0x7D is 125 in hex, so the commit message needs to be fixed.


Cheers
Jack Wang

Re: [PATCH 3/3] target/i386: modify Icelake-Client and Icelake-Server CPU model number

[Chenyi Qiang]

On 2/27/2020 5:48 PM, Jack Wang wrote:
> Chenyi Qiang <chenyi.qiang@intel.com> 于2020年2月27日周四 上午10:07写道：
>>
>> According to the Intel Icelake family list, Icelake-Client uses model
>> number 126(0x7D)
> 0x7D is 125 in hex, so the commit message needs to be fixed.
> 

Sorry, my mistake.

> 
> Cheers
> Jack Wang
> 

Re: [PATCH 0/3] Fix Skylake, Cascadelake and Icelake Server CPU models

[Chenyi Qiang]

Ping.

On 2/27/2020 5:08 PM, Chenyi Qiang wrote:
> Current Skylake-Server, Cascadelake-Server and Icelake-Server CPU models
> lack several VMX features. Icelake-Server also lacks two features in
> FEAT_7_0_EBX. In addition, The model numbers of Icelake-Client and
> Icelake-Server need to be fixed.
> 
> Chenyi Qiang (3):
>    target/i386: add missing vmx features for several CPU models
>    target/i386: add two missing features for Icelake-Server CPU model
>    target/i386: modify Icelake-Client and Icelake-Server CPU model number
> 
>   target/i386/cpu.c | 13 +++++++++----
>   1 file changed, 9 insertions(+), 4 deletions(-)
> 

Re: [PATCH 0/3] Fix Skylake, Cascadelake and Icelake Server CPU models

[Chenyi Qiang]

Hi Paolo and Eduardo,

It seems I need to put the missing feature bits in the new version of 
CPU model. I'll resend this patch set.
BTW, what about the missing vmx feature bits? Also put in in new version 
CPU model?

Thanks,
Chenyi

On 3/18/2020 4:02 PM, Chenyi Qiang wrote:
> Ping.
> 
> On 2/27/2020 5:08 PM, Chenyi Qiang wrote:
>> Current Skylake-Server, Cascadelake-Server and Icelake-Server CPU models
>> lack several VMX features. Icelake-Server also lacks two features in
>> FEAT_7_0_EBX. In addition, The model numbers of Icelake-Client and
>> Icelake-Server need to be fixed.
>>
>> Chenyi Qiang (3):
>>    target/i386: add missing vmx features for several CPU models
>>    target/i386: add two missing features for Icelake-Server CPU model
>>    target/i386: modify Icelake-Client and Icelake-Server CPU model number
>>
>>   target/i386/cpu.c | 13 +++++++++----
>>   1 file changed, 9 insertions(+), 4 deletions(-)
>>
>