From: Chenyi Qiang <chenyi.qiang@intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>, Richard Henderson <rth@twiddle.net>
Cc: Xiaoyao Li <xiaoyao.li@intel.com>, qemu-devel@nongnu.org
Subject: [PATCH 3/3] target/i386: modify Icelake-Client and Icelake-Server CPU model number
Date: Thu, 27 Feb 2020 17:08:08 +0800 [thread overview]
Message-ID: <20200227090808.17686-4-chenyi.qiang@intel.com> (raw)
In-Reply-To: <20200227090808.17686-1-chenyi.qiang@intel.com>
According to the Intel Icelake family list, Icelake-Client uses model
number 126(0x7D) and Icelake-Server uses model number 106(0x6A).
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
target/i386/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index c0be0f83b4..b43a479528 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3276,7 +3276,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
- .model = 126,
+ .model = 125,
.stepping = 0,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
@@ -3389,7 +3389,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.level = 0xd,
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
- .model = 134,
+ .model = 106,
.stepping = 0,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
--
2.17.1
next prev parent reply other threads:[~2020-02-27 9:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-27 9:08 [PATCH 0/3] Fix Skylake, Cascadelake and Icelake Server CPU models Chenyi Qiang
2020-02-27 9:08 ` [PATCH 1/3] target/i386: add missing vmx features for several " Chenyi Qiang
2020-02-27 9:08 ` [PATCH 2/3] target/i386: add two missing features for Icelake-Server CPU model Chenyi Qiang
2020-02-27 9:08 ` Chenyi Qiang [this message]
2020-02-27 9:48 ` [PATCH 3/3] target/i386: modify Icelake-Client and Icelake-Server CPU model number Jack Wang
2020-02-28 0:30 ` Chenyi Qiang
2020-03-18 8:02 ` [PATCH 0/3] Fix Skylake, Cascadelake and Icelake Server CPU models Chenyi Qiang
2020-03-27 7:45 ` Chenyi Qiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200227090808.17686-4-chenyi.qiang@intel.com \
--to=chenyi.qiang@intel.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=rth@twiddle.net \
--cc=xiaoyao.li@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).