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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 00/12] target/arm: Honor more HCR_EL2 traps Date: Fri, 28 Feb 2020 17:27:59 -0800 Message-Id: <20200229012811.24129-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Changes for v5: * Patch 1 was broken for aa32. Not just the masking vs the "other" 32-bit register that Peter noticed, but more explicitly in that "ri" was dereferenced as NULL -- hcr_write{high,low} did not pass along the structure. Oops. Break out a new helper that is passed a starting mask, which is used to preserve bits from the "other" 32-bit register. Check the aa64 isar registers only if aarch64 is enabled. * Add HCR bits from armv8.6. * Remove EL2 & EL3 from user-only. * Mask hcr_el2 bits that are res0 in aa32. This didn't work at first because we weren't configuring SCR_RW for user-only, so aarch64-linux-user thought EL2 was aa32, which disabled pauth. Rather than find other corner cases like this, I think it makes more sense for user-only to only contend with EL1. Patches 1-5, 12 require review. r~ Richard Henderson (12): target/arm: Improve masking of HCR/HCR2 RES0 bits target/arm: Add HCR_EL2 bit definitions from ARMv8.6 target/arm: Disable has_el2 and has_el3 for user-only target/arm: Remove EL2 and EL3 setup from user-only target/arm: Improve masking in arm_hcr_el2_eff target/arm: Honor the HCR_EL2.{TVM,TRVM} bits target/arm: Honor the HCR_EL2.TSW bit target/arm: Honor the HCR_EL2.TACR bit target/arm: Honor the HCR_EL2.TPCP bit target/arm: Honor the HCR_EL2.TPU bit target/arm: Honor the HCR_EL2.TTLB bit tests/tcg/aarch64: Add newline in pauth-1 printf target/arm/cpu.h | 7 + target/arm/cpu.c | 12 +- target/arm/helper.c | 358 +++++++++++++++++++++++++----------- tests/tcg/aarch64/pauth-1.c | 2 +- 4 files changed, 262 insertions(+), 117 deletions(-) -- 2.20.1