From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH v5 08/12] target/arm: Honor the HCR_EL2.TACR bit
Date: Fri, 28 Feb 2020 17:28:07 -0800 [thread overview]
Message-ID: <20200229012811.24129-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org>
This bit traps EL1 access to the auxiliary control registers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ddef3d7dc3..2c06ac8d02 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -553,6 +553,16 @@ static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
+/* Check for traps from EL1 due to HCR_EL2.TACR. */
+static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TACR)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ return CP_ACCESS_OK;
+}
+
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = env_archcpu(env);
@@ -6961,8 +6971,8 @@ static const ARMCPRegInfo ats1cp_reginfo[] = {
static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = {
{ .name = "ACTLR2", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST,
- .resetvalue = 0 },
+ .access = PL1_RW, .accessfn = access_tacr,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "HACTLR2", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 3,
.access = PL2_RW, .type = ARM_CP_CONST,
@@ -7718,8 +7728,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPRegInfo auxcr_reginfo[] = {
{ .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST,
- .resetvalue = cpu->reset_auxcr },
+ .access = PL1_RW, .accessfn = access_tacr,
+ .type = ARM_CP_CONST, .resetvalue = cpu->reset_auxcr },
{ .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_CONST,
--
2.20.1
next prev parent reply other threads:[~2020-02-29 1:33 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-29 1:27 [PATCH v5 00/12] target/arm: Honor more HCR_EL2 traps Richard Henderson
2020-02-29 1:28 ` [PATCH v5 01/12] target/arm: Improve masking of HCR/HCR2 RES0 bits Richard Henderson
2020-02-29 1:28 ` [PATCH v5 02/12] target/arm: Add HCR_EL2 bit definitions from ARMv8.6 Richard Henderson
2020-02-29 1:28 ` [PATCH v5 03/12] target/arm: Disable has_el2 and has_el3 for user-only Richard Henderson
2020-02-29 1:28 ` [PATCH v5 04/12] target/arm: Remove EL2 and EL3 setup from user-only Richard Henderson
2020-02-29 1:28 ` [PATCH v5 05/12] target/arm: Improve masking in arm_hcr_el2_eff Richard Henderson
2020-02-29 1:28 ` [PATCH v5 06/12] target/arm: Honor the HCR_EL2.{TVM,TRVM} bits Richard Henderson
2020-02-29 1:28 ` [PATCH v5 07/12] target/arm: Honor the HCR_EL2.TSW bit Richard Henderson
2020-02-29 1:28 ` Richard Henderson [this message]
2020-02-29 1:28 ` [PATCH v5 09/12] target/arm: Honor the HCR_EL2.TPCP bit Richard Henderson
2020-02-29 1:28 ` [PATCH v5 10/12] target/arm: Honor the HCR_EL2.TPU bit Richard Henderson
2020-02-29 1:28 ` [PATCH v5 11/12] target/arm: Honor the HCR_EL2.TTLB bit Richard Henderson
2020-02-29 1:28 ` [PATCH v5 12/12] tests/tcg/aarch64: Add newline in pauth-1 printf Richard Henderson
2020-03-02 15:22 ` [PATCH v5 00/12] target/arm: Honor more HCR_EL2 traps Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200229012811.24129-9-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).