From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH v2 4/9] target/arm: Apply TBI to ESR_ELx in helper_exception_return
Date: Mon, 2 Mar 2020 09:58:24 -0800 [thread overview]
Message-ID: <20200302175829.2183-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200302175829.2183-1-richard.henderson@linaro.org>
We missed this case within AArch64.ExceptionReturn.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-a64.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 509ae93069..123ce50e7a 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -1031,6 +1031,8 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
"AArch32 EL%d PC 0x%" PRIx32 "\n",
cur_el, new_el, env->regs[15]);
} else {
+ int tbii;
+
env->aarch64 = 1;
spsr &= aarch64_pstate_valid_mask(&env_archcpu(env)->isar);
pstate_write(env, spsr);
@@ -1038,8 +1040,27 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
env->pstate &= ~PSTATE_SS;
}
aarch64_restore_sp(env, new_el);
- env->pc = new_pc;
helper_rebuild_hflags_a64(env, new_el);
+
+ /*
+ * Apply TBI to the exception return address. We had to delay this
+ * until after we selected the new EL, so that we could select the
+ * correct TBI+TBID bits. This is made easier by waiting until after
+ * the hflags rebuild, since we can pull the composite TBII field
+ * from there.
+ */
+ tbii = FIELD_EX32(env->hflags, TBFLAG_A64, TBII);
+ if ((tbii >> extract64(new_pc, 55, 1)) & 1) {
+ /* TBI is enabled. */
+ int core_mmu_idx = cpu_mmu_index(env, false);
+ if (regime_has_2_ranges(core_to_aa64_mmu_idx(core_mmu_idx))) {
+ new_pc = sextract64(new_pc, 0, 56);
+ } else {
+ new_pc = extract64(new_pc, 0, 56);
+ }
+ }
+ env->pc = new_pc;
+
qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
"AArch64 EL%d PC 0x%" PRIx64 "\n",
cur_el, new_el, env->pc);
--
2.20.1
next prev parent reply other threads:[~2020-03-02 18:00 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-02 17:58 [PATCH v2 0/9] target/arm: Misc cleanups surrounding TBI Richard Henderson
2020-03-02 17:58 ` [PATCH v2 1/9] target/arm: Replicate TBI/TBID bits for single range regimes Richard Henderson
2020-03-02 23:51 ` Philippe Mathieu-Daudé
2020-03-02 17:58 ` [PATCH v2 2/9] target/arm: Optimize cpu_mmu_index Richard Henderson
2020-03-05 14:23 ` Peter Maydell
2020-03-02 17:58 ` [PATCH v2 3/9] target/arm: Introduce core_to_aa64_mmu_idx Richard Henderson
2020-03-02 23:50 ` Philippe Mathieu-Daudé
2020-03-05 14:23 ` Peter Maydell
2020-03-02 17:58 ` Richard Henderson [this message]
2020-03-05 14:24 ` [PATCH v2 4/9] target/arm: Apply TBI to ESR_ELx in helper_exception_return Peter Maydell
2020-03-02 17:58 ` [PATCH v2 5/9] target/arm: Move helper_dc_zva to helper-a64.c Richard Henderson
2020-03-02 23:52 ` Philippe Mathieu-Daudé
2020-03-02 17:58 ` [PATCH v2 6/9] target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva Richard Henderson
2020-03-02 23:53 ` Philippe Mathieu-Daudé
2020-03-02 17:58 ` [PATCH v2 7/9] target/arm: Clean address for DC ZVA Richard Henderson
2020-03-02 17:58 ` [PATCH v2 8/9] target/arm: Check addresses for disabled regimes Richard Henderson
2020-03-05 14:21 ` Peter Maydell
2020-03-05 15:57 ` Richard Henderson
2020-03-02 17:58 ` [PATCH v2 9/9] target/arm: Disable clean_data_tbi for system mode Richard Henderson
2020-03-05 15:12 ` [PATCH v2 0/9] target/arm: Misc cleanups surrounding TBI Peter Maydell
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