From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: richard.henderson@linaro.org, alistair23@gmail.com,
chihmin.chao@sifive.com, palmer@dabbelt.com
Cc: guoren@linux.alibaba.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v3 48/60] target/riscv: vector mask-register logical instructions
Date: Mon, 9 Mar 2020 16:20:30 +0800 [thread overview]
Message-ID: <20200309082042.12967-49-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200309082042.12967-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 9 ++++++
target/riscv/insn32.decode | 8 +++++
target/riscv/insn_trans/trans_rvv.inc.c | 28 +++++++++++++++++
target/riscv/vector_helper.c | 40 +++++++++++++++++++++++++
4 files changed, 85 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index b0bb617b42..9301ce0e00 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1074,3 +1074,12 @@ DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmandnot_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmxor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index f1efc8886d..76a9bae8bb 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -539,6 +539,14 @@ vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
# Vector widening ordered and unordered float reduction sum
vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm
+vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
+vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
+vmandnot_mm 011000 - ..... ..... 010 ..... 1010111 @r
+vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r
+vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
+vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
+vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r
+vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index ad864c9742..065b415abb 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2052,3 +2052,31 @@ GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
/* Vector Widening Floating-Point Reduction Instructions */
GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
+
+/*
+ *** Vector Mask Operations
+ */
+/* Vector Mask-Register Logical Instructions */
+#define GEN_MM_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_r *a) \
+{ \
+ if (vext_check_isa_ill(s, RVV)) { \
+ uint32_t data = 0; \
+ gen_helper_gvec_4_ptr * fn = gen_helper_##NAME; \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), \
+ cpu_env, 0, s->vlen / 8, data, fn); \
+ return true; \
+ } \
+ return false; \
+}
+GEN_MM_TRANS(vmand_mm)
+GEN_MM_TRANS(vmnand_mm)
+GEN_MM_TRANS(vmandnot_mm)
+GEN_MM_TRANS(vmxor_mm)
+GEN_MM_TRANS(vmor_mm)
+GEN_MM_TRANS(vmnor_mm)
+GEN_MM_TRANS(vmornot_mm)
+GEN_MM_TRANS(vmxnor_mm)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index d325fe5e2e..9e9d172cda 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4238,3 +4238,43 @@ void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
clearq(vd, 1, sizeof(uint64_t), tot);
}
}
+
+/*
+ *** Vector Mask Operations
+ */
+/* Vector Mask-Register Logical Instructions */
+#define GEN_VEXT_MASK_VV(NAME, OP) \
+void HELPER(NAME)(void *vd, void *v0, void *vs1, \
+ void *vs2, CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t mlen = vext_mlen(desc); \
+ uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ int a, b; \
+ for (i = 0; i < vl; i++) { \
+ a = vext_elem_mask(vs1, mlen, i); \
+ b = vext_elem_mask(vs2, mlen, i); \
+ vext_set_elem_mask(vd, mlen, i, OP(b, a)); \
+ } \
+ if (i == 0) { \
+ return; \
+ } \
+ for (; i < vlmax; i++) { \
+ vext_set_elem_mask(vd, mlen, i, 0); \
+ } \
+}
+#define DO_NAND(N, M) (!(N & M))
+#define DO_ANDNOT(N, M) (N & !M)
+#define DO_NOR(N, M) (!(N | M))
+#define DO_ORNOT(N, M) (N | !M)
+#define DO_XNOR(N, M) (!(N ^ M))
+
+GEN_VEXT_MASK_VV(vmand_mm, DO_AND)
+GEN_VEXT_MASK_VV(vmnand_mm, DO_NAND)
+GEN_VEXT_MASK_VV(vmandnot_mm, DO_ANDNOT)
+GEN_VEXT_MASK_VV(vmxor_mm, DO_XOR)
+GEN_VEXT_MASK_VV(vmor_mm, DO_OR)
+GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR)
+GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT)
+GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR)
--
2.23.0
next prev parent reply other threads:[~2020-03-09 8:39 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-09 8:19 [PATCH v3 00/60] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 02/60] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 03/60] target/riscv: support vector extension csr LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 04/60] target/riscv: add vector configure instruction LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 05/60] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 06/60] target/riscv: add vector index " LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 07/60] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 08/60] target/riscv: add vector amo operations LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 09/60] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 10/60] target/riscv: vector widening " LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 12/60] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 13/60] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 14/60] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 15/60] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-03-09 8:19 ` [PATCH v3 17/60] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 18/60] target/riscv: vector integer divide instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 19/60] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 20/60] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 21/60] target/riscv: vector widening " LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 22/60] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 23/60] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 24/60] target/riscv: vector single-width averaging " LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 26/60] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 27/60] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 28/60] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 29/60] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 30/60] target/riscv: vector widening " LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 31/60] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 32/60] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 34/60] target/riscv: vector widening " LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 35/60] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 36/60] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 37/60] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 38/60] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 39/60] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 40/60] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 41/60] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 42/60] target/riscv: widening " LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 43/60] target/riscv: narrowing " LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 45/60] target/riscv: vector wideing integer reduction instructions LIU Zhiwei
2020-03-09 8:20 ` LIU Zhiwei [this message]
-- strict thread matches above, loose matches on Subject: below --
2020-03-09 12:05 [PATCH v3 16/60] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-03-09 12:05 ` [PATCH v3 48/60] target/riscv: vector mask-register logical instructions LIU Zhiwei
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