From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: richard.henderson@linaro.org, alistair23@gmail.com,
chihmin.chao@sifive.com, palmer@dabbelt.com
Cc: guoren@linux.alibaba.com, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v3 32/60] target/riscv: vector widening floating-point multiply
Date: Mon, 9 Mar 2020 20:14:29 +0800 [thread overview]
Message-ID: <20200309121457.13719-33-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200309121457.13719-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 5 +++++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 4 ++++
target/riscv/vector_helper.c | 22 ++++++++++++++++++++++
4 files changed, 33 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a2d7ed19a8..3ec2dcadd4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -834,3 +834,8 @@ DEF_HELPER_6(vfdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfrdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfrdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfrdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_6(vfwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwmul_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfwmul_vf_w, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 050b2fd467..e0ee8f5a7c 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -456,6 +456,8 @@ vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm
vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm
vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm
vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm
+vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm
+vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 8dcbff6c64..b4d3797685 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1802,3 +1802,7 @@ GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check)
GEN_OPFVF_TRANS(vfmul_vf, opfvf_check)
GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check)
GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
+
+/* Vector Widening Floating-Point Multiply */
+GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
+GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index bd7ee4de18..8bb6ac158f 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3154,3 +3154,25 @@ RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv)
GEN_VEXT_VF(vfrdiv_vf_h, 2, 2, clearh)
GEN_VEXT_VF(vfrdiv_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfrdiv_vf_d, 8, 8, clearq)
+
+/* Vector Widening Floating-Point Multiply */
+static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
+{
+ return float32_mul(float16_to_float32(a, true, s),
+ float16_to_float32(b, true, s), s);
+}
+
+static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
+{
+ return float64_mul(float32_to_float64(a, s),
+ float32_to_float64(b, s), s);
+
+}
+RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
+RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32)
+GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4, clearl)
+GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8, clearq)
+RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
+RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
+GEN_VEXT_VF(vfwmul_vf_h, 2, 4, clearl)
+GEN_VEXT_VF(vfwmul_vf_w, 4, 8, clearq)
--
2.23.0
next prev parent reply other threads:[~2020-03-09 12:42 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-09 12:13 [PATCH v3 00/60] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-03-09 12:13 ` [PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-03-09 12:13 ` [PATCH v3 02/60] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 03/60] target/riscv: support vector extension csr LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 04/60] target/riscv: add vector configure instruction LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 05/60] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 06/60] target/riscv: add vector index " LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 07/60] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 08/60] target/riscv: add vector amo operations LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 09/60] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 10/60] target/riscv: vector widening " LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 12/60] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 14/60] target/riscv: vector narrowing integer right shift instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 17/60] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 18/60] target/riscv: vector integer divide instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 19/60] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 20/60] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 21/60] target/riscv: vector widening " LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 22/60] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 23/60] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 24/60] target/riscv: vector single-width averaging " LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 25/60] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 26/60] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 27/60] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 28/60] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 29/60] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 30/60] target/riscv: vector widening " LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 31/60] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-03-09 12:14 ` LIU Zhiwei [this message]
2020-03-09 12:14 ` [PATCH v3 33/60] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 35/60] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-03-09 12:14 ` [PATCH v3 37/60] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
-- strict thread matches above, loose matches on Subject: below --
2020-03-09 8:19 [PATCH v3 00/60] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-03-09 8:20 ` [PATCH v3 32/60] target/riscv: vector widening floating-point multiply LIU Zhiwei
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