From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Subject: [PATCH v6 25/42] target/arm: Implement helper_mte_check1
Date: Thu, 12 Mar 2020 12:42:02 -0700 [thread overview]
Message-ID: <20200312194219.24406-26-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200312194219.24406-1-richard.henderson@linaro.org>
Fill out the stub that was added earlier.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 47 +++++++++++++++
target/arm/mte_helper.c | 126 +++++++++++++++++++++++++++++++++++++++-
2 files changed, 172 insertions(+), 1 deletion(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index a993e8ca0a..8bbaf9b453 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1314,6 +1314,9 @@ FIELD(MTEDESC, WRITE, 8, 1)
FIELD(MTEDESC, ESIZE, 9, 5)
FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */
+bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
+uint64_t mte_check1(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra);
+
static inline int allocation_tag_from_addr(uint64_t ptr)
{
return extract64(ptr, 56, 4);
@@ -1324,4 +1327,48 @@ static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag)
return deposit64(ptr, 56, 4, rtag);
}
+/* Return true if tbi bits mean that the access is checked. */
+static inline bool tbi_check(uint32_t desc, int bit55)
+{
+ return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1;
+}
+
+/* Return true if tcma bits mean that the access is unchecked. */
+static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag)
+{
+ /*
+ * We had extracted bit55 and ptr_tag for other reasons, so fold
+ * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test.
+ */
+ bool match = ((ptr_tag + bit55) & 0xf) == 0;
+ bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1;
+ return tcma && match;
+}
+
+/*
+ * For TBI, ideally, we would do nothing. Proper behaviour on fault is
+ * for the tag to be present in the FAR_ELx register. But for user-only
+ * mode, we do not have a TLB with which to implement this, so we must
+ * remote the top byte.
+ */
+static inline uint64_t useronly_clean_ptr(uint64_t ptr)
+{
+ /* TBI is known to be enabled. */
+#ifdef CONFIG_USER_ONLY
+ ptr = sextract64(ptr, 0, 56);
+#endif
+ return ptr;
+}
+
+static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr)
+{
+#ifdef CONFIG_USER_ONLY
+ int64_t clean_ptr = sextract64(ptr, 0, 56);
+ if (tbi_check(desc, clean_ptr < 0)) {
+ ptr = clean_ptr;
+ }
+#endif
+ return ptr;
+}
+
#endif
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 907a12b366..7a87574b35 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -359,12 +359,136 @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
}
}
+/* Record a tag check failure. */
+static void mte_check_fail(CPUARMState *env, int mmu_idx,
+ uint64_t dirty_ptr, uintptr_t ra)
+{
+ ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
+ int el, reg_el, tcf, select;
+ uint64_t sctlr;
+
+ reg_el = regime_el(env, arm_mmu_idx);
+ sctlr = env->cp15.sctlr_el[reg_el];
+
+ switch (arm_mmu_idx) {
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E20_0:
+ el = 0;
+ tcf = extract64(sctlr, 38, 2);
+ break;
+ default:
+ el = reg_el;
+ tcf = extract64(sctlr, 40, 2);
+ }
+
+ switch (tcf) {
+ case 1:
+ /*
+ * Tag check fail causes a synchronous exception.
+ *
+ * In restore_state_to_opc, we set the exception syndrome
+ * for the load or store operation. Unwind first so we
+ * may overwrite that with the syndrome for the tag check.
+ */
+ cpu_restore_state(env_cpu(env), ra, true);
+ env->exception.vaddress = dirty_ptr;
+ raise_exception(env, EXCP_DATA_ABORT,
+ syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0x11),
+ exception_target_el(env));
+ /* noreturn, but fall through to the assert anyway */
+
+ case 0:
+ /*
+ * Tag check fail does not affect the PE.
+ * We eliminate this case by not setting MTE_ACTIVE
+ * in tb_flags, so that we never make this runtime call.
+ */
+ g_assert_not_reached();
+
+ case 2:
+ /* Tag check fail causes asynchronous flag set. */
+ mmu_idx = arm_mmu_idx_el(env, el);
+ if (regime_has_2_ranges(mmu_idx)) {
+ select = extract64(dirty_ptr, 55, 1);
+ } else {
+ select = 0;
+ }
+ env->cp15.tfsr_el[el] |= 1 << select;
+ break;
+
+ default:
+ /* Case 3: Reserved. */
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Tag check failure with SCTLR_EL%d.TCF%s "
+ "set to reserved value %d\n",
+ reg_el, el ? "" : "0", tcf);
+ break;
+ }
+}
+
/*
* Perform an MTE checked access for a single logical or atomic access.
*/
+static bool mte_probe1_int(CPUARMState *env, uint32_t desc, uint64_t ptr,
+ uintptr_t ra, int bit55)
+{
+ int mem_tag, mmu_idx, ptr_tag, size;
+ MMUAccessType type;
+ uint8_t *mem;
+
+ ptr_tag = allocation_tag_from_addr(ptr);
+
+ if (tcma_check(desc, bit55, ptr_tag)) {
+ return true;
+ }
+
+ mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
+ type = FIELD_EX32(desc, MTEDESC, WRITE) ? MMU_DATA_STORE : MMU_DATA_LOAD;
+ size = FIELD_EX32(desc, MTEDESC, ESIZE);
+
+ mem = allocation_tag_mem(env, mmu_idx, ptr, type, size,
+ MMU_DATA_LOAD, 1, ra);
+ if (!mem) {
+ return true;
+ }
+
+ mem_tag = load_tag1(ptr, mem);
+ return ptr_tag == mem_tag;
+}
+
+/* No-fault version of mte_check1, to be used by SVE for MemSingleNF. */
+bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra)
+{
+ int bit55 = extract64(ptr, 55, 1);
+
+ /* If TBI is disabled, the access is unchecked. */
+ if (unlikely(!tbi_check(desc, bit55))) {
+ return true;
+ }
+
+ return mte_probe1_int(env, desc, ptr, ra, bit55);
+}
+
+uint64_t mte_check1(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra)
+{
+ int bit55 = extract64(ptr, 55, 1);
+
+ /* If TBI is disabled, the access is unchecked, and ptr is not dirty. */
+ if (unlikely(!tbi_check(desc, bit55))) {
+ return ptr;
+ }
+
+ if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) {
+ int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
+ mte_check_fail(env, mmu_idx, ptr, ra);
+ }
+
+ return useronly_clean_ptr(ptr);
+}
+
uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr)
{
- return ptr;
+ return mte_check1(env, desc, ptr, GETPC());
}
/*
--
2.20.1
next prev parent reply other threads:[~2020-03-12 20:03 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 19:41 [PATCH v6 00/42] target/arm: Implement ARMv8.5-MemTag, system mode Richard Henderson
2020-03-12 19:41 ` [PATCH v6 01/42] target/arm: Add isar tests for mte Richard Henderson
2020-03-12 19:41 ` [PATCH v6 02/42] target/arm: Improve masking of SCR RES0 bits Richard Henderson
2020-03-12 19:41 ` [PATCH v6 03/42] target/arm: Add support for MTE to SCTLR_ELx Richard Henderson
2020-03-12 19:41 ` [PATCH v6 04/42] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 Richard Henderson
2020-03-12 19:41 ` [PATCH v6 05/42] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT Richard Henderson
2020-03-12 19:41 ` [PATCH v6 06/42] target/arm: Add DISAS_UPDATE_NOCHAIN Richard Henderson
2020-03-12 19:41 ` [PATCH v6 07/42] target/arm: Add MTE system registers Richard Henderson
2020-03-12 19:41 ` [PATCH v6 08/42] target/arm: Add MTE bits to tb_flags Richard Henderson
2020-03-12 19:41 ` [PATCH v6 09/42] target/arm: Implement the IRG instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 10/42] target/arm: Implement the ADDG, SUBG instructions Richard Henderson
2020-03-12 19:41 ` [PATCH v6 11/42] target/arm: Implement the GMI instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 12/42] target/arm: Implement the SUBP instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 13/42] target/arm: Define arm_cpu_do_unaligned_access for user-only Richard Henderson
2020-03-12 19:41 ` [PATCH v6 14/42] target/arm: Add helper_probe_access Richard Henderson
2020-03-12 19:41 ` [PATCH v6 15/42] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2020-03-12 19:41 ` [PATCH v6 16/42] target/arm: Implement the STGP instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 17/42] target/arm: Restrict the values of DCZID.BS under TCG Richard Henderson
2020-03-12 19:41 ` [PATCH v6 18/42] target/arm: Simplify DC_ZVA Richard Henderson
2020-03-12 19:41 ` [PATCH v6 19/42] target/arm: Implement the LDGM, STGM, STZGM instructions Richard Henderson
2020-03-12 19:41 ` [PATCH v6 20/42] target/arm: Implement the access tag cache flushes Richard Henderson
2020-03-12 19:41 ` [PATCH v6 21/42] target/arm: Move regime_el to internals.h Richard Henderson
2020-03-12 19:41 ` [PATCH v6 22/42] target/arm: Move regime_tcr " Richard Henderson
2020-03-12 19:42 ` [PATCH v6 23/42] target/arm: Add gen_mte_check1 Richard Henderson
2020-03-12 19:42 ` [PATCH v6 24/42] target/arm: Add gen_mte_checkN Richard Henderson
2020-03-12 19:42 ` Richard Henderson [this message]
2020-03-12 19:42 ` [PATCH v6 26/42] target/arm: Implement helper_mte_checkN Richard Henderson
2020-03-12 19:42 ` [PATCH v6 27/42] target/arm: Add helper_mte_check_zva Richard Henderson
2020-03-12 19:42 ` [PATCH v6 28/42] target/arm: Use mte_checkN for sve unpredicated loads Richard Henderson
2020-03-12 19:42 ` [PATCH v6 29/42] target/arm: Use mte_checkN for sve unpredicated stores Richard Henderson
2020-03-12 19:42 ` [PATCH v6 30/42] target/arm: Use mte_check1 for sve LD1R Richard Henderson
2020-03-12 19:42 ` [PATCH v6 31/42] target/arm: Add mte helpers for sve scalar + int loads Richard Henderson
2020-03-12 19:42 ` [PATCH v6 32/42] target/arm: Add mte helpers for sve scalar + int stores Richard Henderson
2020-03-12 19:42 ` [PATCH v6 33/42] target/arm: Add mte helpers for sve scalar + int ff/nf loads Richard Henderson
2020-03-12 19:42 ` [PATCH v6 34/42] target/arm: Handle TBI for sve scalar + int memory ops Richard Henderson
2020-03-12 19:42 ` [PATCH v6 35/42] target/arm: Add mte helpers for sve scatter/gather " Richard Henderson
2020-03-12 19:42 ` [PATCH v6 36/42] target/arm: Complete TBI clearing for user-only for SVE Richard Henderson
2020-03-12 19:42 ` [PATCH v6 37/42] target/arm: Implement data cache set allocation tags Richard Henderson
2020-03-12 19:42 ` [PATCH v6 38/42] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2020-03-12 19:42 ` [PATCH v6 39/42] target/arm: Enable MTE Richard Henderson
2020-03-12 19:42 ` [PATCH v6 40/42] target/arm: Cache the Tagged bit for a page in MemTxAttrs Richard Henderson
2020-03-12 19:42 ` [PATCH v6 41/42] target/arm: Create tagged ram when MTE is enabled Richard Henderson
2020-03-12 19:42 ` [PATCH v6 42/42] target/arm: Add allocation tag storage for system mode Richard Henderson
2020-05-18 14:46 ` [PATCH v6 00/42] target/arm: Implement ARMv8.5-MemTag, " Peter Maydell
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