From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Subject: [PATCH v6 40/42] target/arm: Cache the Tagged bit for a page in MemTxAttrs
Date: Thu, 12 Mar 2020 12:42:17 -0700 [thread overview]
Message-ID: <20200312194219.24406-41-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200312194219.24406-1-richard.henderson@linaro.org>
This "bit" is a particular value of the page's MemAttr.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v6: Test HCR_EL2.{DC,DCT}; test Stage2 attributes.
---
target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++--------
1 file changed, 35 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b38dc74733..c272c48467 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10785,6 +10785,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
uint64_t descaddrmask;
bool aarch64 = arm_el_is_aa64(env, el);
bool guarded = false;
+ uint8_t memattr;
/* TODO:
* This code does not handle the different format TCR for VTCR_EL2.
@@ -11013,17 +11014,32 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
txattrs->target_tlb_bit0 = true;
}
- if (cacheattrs != NULL) {
+ if (mmu_idx == ARMMMUIdx_Stage2) {
+ memattr = convert_stage2_attrs(env, extract32(attrs, 0, 4));
+ } else {
+ /* Index into MAIR registers for cache attributes */
+ uint64_t mair = env->cp15.mair_el[el];
+ memattr = extract64(mair, extract32(attrs, 0, 3) * 8, 8);
+ }
+
+ /* When MTE is enabled, remember Tagged Memory in IOTLB. */
+ if (aarch64 && cpu_isar_feature(aa64_mte, cpu)) {
if (mmu_idx == ARMMMUIdx_Stage2) {
- cacheattrs->attrs = convert_stage2_attrs(env,
- extract32(attrs, 0, 4));
+ /*
+ * Require Normal, I+O Shareable, WB, NT, RA, WA (0xff).
+ * If not, squash stage1 tagged normal setting.
+ */
+ if (memattr != 0xff) {
+ txattrs->target_tlb_bit1 = false;
+ }
} else {
- /* Index into MAIR registers for cache attributes */
- uint8_t attrindx = extract32(attrs, 0, 3);
- uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
- assert(attrindx <= 7);
- cacheattrs->attrs = extract64(mair, attrindx * 8, 8);
+ /* Tagged Normal Memory (0xf0). */
+ txattrs->target_tlb_bit1 = (memattr == 0xf0);
}
+ }
+
+ if (cacheattrs != NULL) {
+ cacheattrs->attrs = memattr;
cacheattrs->shareability = extract32(attrs, 6, 2);
}
@@ -11978,6 +11994,17 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
*phys_ptr = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
*page_size = TARGET_PAGE_SIZE;
+
+ /* Stage1 translations are Tagged or Untagged based on HCR_DCT. */
+ if (cpu_isar_feature(aa64_mte, env_archcpu(env))
+ && (mmu_idx == ARMMMUIdx_Stage1_E0 ||
+ mmu_idx == ARMMMUIdx_Stage1_E1 ||
+ mmu_idx == ARMMMUIdx_Stage1_E1_PAN)) {
+ uint64_t hcr = arm_hcr_el2_eff(env);
+ if ((hcr & (HCR_DC | HCR_DCT)) == (HCR_DC | HCR_DCT)) {
+ attrs->target_tlb_bit1 = true;
+ }
+ }
return 0;
}
--
2.20.1
next prev parent reply other threads:[~2020-03-12 19:55 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 19:41 [PATCH v6 00/42] target/arm: Implement ARMv8.5-MemTag, system mode Richard Henderson
2020-03-12 19:41 ` [PATCH v6 01/42] target/arm: Add isar tests for mte Richard Henderson
2020-03-12 19:41 ` [PATCH v6 02/42] target/arm: Improve masking of SCR RES0 bits Richard Henderson
2020-03-12 19:41 ` [PATCH v6 03/42] target/arm: Add support for MTE to SCTLR_ELx Richard Henderson
2020-03-12 19:41 ` [PATCH v6 04/42] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 Richard Henderson
2020-03-12 19:41 ` [PATCH v6 05/42] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT Richard Henderson
2020-03-12 19:41 ` [PATCH v6 06/42] target/arm: Add DISAS_UPDATE_NOCHAIN Richard Henderson
2020-03-12 19:41 ` [PATCH v6 07/42] target/arm: Add MTE system registers Richard Henderson
2020-03-12 19:41 ` [PATCH v6 08/42] target/arm: Add MTE bits to tb_flags Richard Henderson
2020-03-12 19:41 ` [PATCH v6 09/42] target/arm: Implement the IRG instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 10/42] target/arm: Implement the ADDG, SUBG instructions Richard Henderson
2020-03-12 19:41 ` [PATCH v6 11/42] target/arm: Implement the GMI instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 12/42] target/arm: Implement the SUBP instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 13/42] target/arm: Define arm_cpu_do_unaligned_access for user-only Richard Henderson
2020-03-12 19:41 ` [PATCH v6 14/42] target/arm: Add helper_probe_access Richard Henderson
2020-03-12 19:41 ` [PATCH v6 15/42] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2020-03-12 19:41 ` [PATCH v6 16/42] target/arm: Implement the STGP instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 17/42] target/arm: Restrict the values of DCZID.BS under TCG Richard Henderson
2020-03-12 19:41 ` [PATCH v6 18/42] target/arm: Simplify DC_ZVA Richard Henderson
2020-03-12 19:41 ` [PATCH v6 19/42] target/arm: Implement the LDGM, STGM, STZGM instructions Richard Henderson
2020-03-12 19:41 ` [PATCH v6 20/42] target/arm: Implement the access tag cache flushes Richard Henderson
2020-03-12 19:41 ` [PATCH v6 21/42] target/arm: Move regime_el to internals.h Richard Henderson
2020-03-12 19:41 ` [PATCH v6 22/42] target/arm: Move regime_tcr " Richard Henderson
2020-03-12 19:42 ` [PATCH v6 23/42] target/arm: Add gen_mte_check1 Richard Henderson
2020-03-12 19:42 ` [PATCH v6 24/42] target/arm: Add gen_mte_checkN Richard Henderson
2020-03-12 19:42 ` [PATCH v6 25/42] target/arm: Implement helper_mte_check1 Richard Henderson
2020-03-12 19:42 ` [PATCH v6 26/42] target/arm: Implement helper_mte_checkN Richard Henderson
2020-03-12 19:42 ` [PATCH v6 27/42] target/arm: Add helper_mte_check_zva Richard Henderson
2020-03-12 19:42 ` [PATCH v6 28/42] target/arm: Use mte_checkN for sve unpredicated loads Richard Henderson
2020-03-12 19:42 ` [PATCH v6 29/42] target/arm: Use mte_checkN for sve unpredicated stores Richard Henderson
2020-03-12 19:42 ` [PATCH v6 30/42] target/arm: Use mte_check1 for sve LD1R Richard Henderson
2020-03-12 19:42 ` [PATCH v6 31/42] target/arm: Add mte helpers for sve scalar + int loads Richard Henderson
2020-03-12 19:42 ` [PATCH v6 32/42] target/arm: Add mte helpers for sve scalar + int stores Richard Henderson
2020-03-12 19:42 ` [PATCH v6 33/42] target/arm: Add mte helpers for sve scalar + int ff/nf loads Richard Henderson
2020-03-12 19:42 ` [PATCH v6 34/42] target/arm: Handle TBI for sve scalar + int memory ops Richard Henderson
2020-03-12 19:42 ` [PATCH v6 35/42] target/arm: Add mte helpers for sve scatter/gather " Richard Henderson
2020-03-12 19:42 ` [PATCH v6 36/42] target/arm: Complete TBI clearing for user-only for SVE Richard Henderson
2020-03-12 19:42 ` [PATCH v6 37/42] target/arm: Implement data cache set allocation tags Richard Henderson
2020-03-12 19:42 ` [PATCH v6 38/42] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2020-03-12 19:42 ` [PATCH v6 39/42] target/arm: Enable MTE Richard Henderson
2020-03-12 19:42 ` Richard Henderson [this message]
2020-03-12 19:42 ` [PATCH v6 41/42] target/arm: Create tagged ram when MTE is enabled Richard Henderson
2020-03-12 19:42 ` [PATCH v6 42/42] target/arm: Add allocation tag storage for system mode Richard Henderson
2020-05-18 14:46 ` [PATCH v6 00/42] target/arm: Implement ARMv8.5-MemTag, " Peter Maydell
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