From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Subject: [PATCH v6 08/42] target/arm: Add MTE bits to tb_flags
Date: Thu, 12 Mar 2020 12:41:45 -0700 [thread overview]
Message-ID: <20200312194219.24406-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200312194219.24406-1-richard.henderson@linaro.org>
Cache the composite ATA setting.
Cache when MTE is fully enabled, i.e. access to tags are enabled
and tag checks affect the PE. Do this for both the normal context
and the UNPRIV context.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Remove stub helper_mte_check; moved to a later patch.
v6: Add mte0_active and ata bits; drop reviewed-by.
---
target/arm/cpu.h | 12 ++++++++----
target/arm/internals.h | 18 +++++++++++++++++
target/arm/translate.h | 5 +++++
target/arm/helper.c | 40 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-a64.c | 4 ++++
5 files changed, 75 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 25351abd15..67164d56a1 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3155,10 +3155,10 @@ typedef ARMCPU ArchCPU;
* | | | TBFLAG_A32 | |
* | | +-----+----------+ TBFLAG_AM32 |
* | TBFLAG_ANY | |TBFLAG_M32| |
- * | | +-+----------+--------------|
- * | | | TBFLAG_A64 |
- * +--------------+---------+---------------------------+
- * 31 20 15 0
+ * | +-----------+----------+--------------|
+ * | | TBFLAG_A64 |
+ * +--------------+-------------------------------------+
+ * 31 20 0
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
@@ -3225,6 +3225,10 @@ FIELD(TBFLAG_A64, BT, 9, 1)
FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
FIELD(TBFLAG_A64, TBID, 12, 2)
FIELD(TBFLAG_A64, UNPRIV, 14, 1)
+FIELD(TBFLAG_A64, ATA, 15, 1)
+FIELD(TBFLAG_A64, TCMA, 16, 2)
+FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
+FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
/**
* cpu_mmu_index:
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 0591f30526..45f445cf3e 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1194,6 +1194,24 @@ static inline int exception_target_el(CPUARMState *env)
return target_el;
}
+/* Determine if allocation tags are available. */
+static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
+ uint64_t sctlr)
+{
+ if (el < 3
+ && arm_feature(env, ARM_FEATURE_EL3)
+ && !(env->cp15.scr_el3 & SCR_ATA)) {
+ return false;
+ }
+ if (el < 2
+ && arm_feature(env, ARM_FEATURE_EL2)
+ && !(arm_hcr_el2_eff(env) & HCR_ATA)) {
+ return false;
+ }
+ sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA);
+ return sctlr != 0;
+}
+
#ifndef CONFIG_USER_ONLY
/* Security attributes for an address, as returned by v8m_security_lookup. */
diff --git a/target/arm/translate.h b/target/arm/translate.h
index dbbb167174..e0f5d0be63 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -30,6 +30,7 @@ typedef struct DisasContext {
ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
uint8_t tbii; /* TBI1|TBI0 for insns */
uint8_t tbid; /* TBI1|TBI0 for data */
+ uint8_t tcma; /* TCMA1|TCMA0 for MTE */
bool ns; /* Use non-secure CPREG bank on access */
int fp_excp_el; /* FP exception EL or 0 if enabled */
int sve_excp_el; /* SVE exception EL or 0 if enabled */
@@ -77,6 +78,10 @@ typedef struct DisasContext {
bool unpriv;
/* True if v8.3-PAuth is active. */
bool pauth_active;
+ /* True if v8.5-MTE access to tags is enabled. */
+ bool ata;
+ /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */
+ bool mte_active[2];
/* True with v8.5-BTI and SCTLR_ELx.BT* set. */
bool bt;
/* True if any CP15 access is trapped by HSTR_EL2 */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b47209be64..01d2fcf2e3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10587,6 +10587,16 @@ static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx)
}
}
+static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
+{
+ if (regime_has_2_ranges(mmu_idx)) {
+ return extract64(tcr, 57, 2);
+ } else {
+ /* Replicate the single TCMA bit so we always have 2 bits. */
+ return extract32(tcr, 30, 1) * 3;
+ }
+}
+
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
ARMMMUIdx mmu_idx, bool data)
{
@@ -12590,6 +12600,36 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
}
}
+ if (cpu_isar_feature(aa64_mte, env_archcpu(env))) {
+ /*
+ * Set MTE_ACTIVE if any access may be Checked, and leave clear
+ * if all accesses must be Unchecked:
+ * 1) If no TBI, then there are no tags in the address to check,
+ * 2) If Tag Check Override, then all accesses are Unchecked,
+ * 3) If Tag Check Fail == 0, then Checked access have no effect,
+ * 4) If no Allocation Tag Access, then all accesses are Unchecked.
+ */
+ if (allocation_tag_access_enabled(env, el, sctlr)) {
+ flags = FIELD_DP32(flags, TBFLAG_A64, ATA, 1);
+ if (tbid
+ && !(env->pstate & PSTATE_TCO)
+ && (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
+ flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1);
+ }
+ }
+ /* And again for unprivileged accesses, if required. */
+ if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)
+ && tbid
+ && !(env->pstate & PSTATE_TCO)
+ && (sctlr & SCTLR_TCF0)
+ && allocation_tag_access_enabled(env, 0, sctlr)) {
+ flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);
+ }
+ /* Cache TCMA as well as TBI. */
+ flags = FIELD_DP32(flags, TBFLAG_A64, TCMA,
+ aa64_va_parameter_tcma(tcr, mmu_idx));
+ }
+
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 528f608408..5eda6ff975 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14335,6 +14335,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx);
dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII);
dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID);
+ dc->tcma = FIELD_EX32(tb_flags, TBFLAG_A64, TCMA);
dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
#if !defined(CONFIG_USER_ONLY)
dc->user = (dc->current_el == 0);
@@ -14346,6 +14347,9 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT);
dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE);
dc->unpriv = FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV);
+ dc->ata = FIELD_EX32(tb_flags, TBFLAG_A64, ATA);
+ dc->mte_active[0] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE);
+ dc->mte_active[1] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE0_ACTIVE);
dc->vec_len = 0;
dc->vec_stride = 0;
dc->cp_regs = arm_cpu->cp_regs;
--
2.20.1
next prev parent reply other threads:[~2020-03-12 19:49 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 19:41 [PATCH v6 00/42] target/arm: Implement ARMv8.5-MemTag, system mode Richard Henderson
2020-03-12 19:41 ` [PATCH v6 01/42] target/arm: Add isar tests for mte Richard Henderson
2020-03-12 19:41 ` [PATCH v6 02/42] target/arm: Improve masking of SCR RES0 bits Richard Henderson
2020-03-12 19:41 ` [PATCH v6 03/42] target/arm: Add support for MTE to SCTLR_ELx Richard Henderson
2020-03-12 19:41 ` [PATCH v6 04/42] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 Richard Henderson
2020-03-12 19:41 ` [PATCH v6 05/42] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT Richard Henderson
2020-03-12 19:41 ` [PATCH v6 06/42] target/arm: Add DISAS_UPDATE_NOCHAIN Richard Henderson
2020-03-12 19:41 ` [PATCH v6 07/42] target/arm: Add MTE system registers Richard Henderson
2020-03-12 19:41 ` Richard Henderson [this message]
2020-03-12 19:41 ` [PATCH v6 09/42] target/arm: Implement the IRG instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 10/42] target/arm: Implement the ADDG, SUBG instructions Richard Henderson
2020-03-12 19:41 ` [PATCH v6 11/42] target/arm: Implement the GMI instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 12/42] target/arm: Implement the SUBP instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 13/42] target/arm: Define arm_cpu_do_unaligned_access for user-only Richard Henderson
2020-03-12 19:41 ` [PATCH v6 14/42] target/arm: Add helper_probe_access Richard Henderson
2020-03-12 19:41 ` [PATCH v6 15/42] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2020-03-12 19:41 ` [PATCH v6 16/42] target/arm: Implement the STGP instruction Richard Henderson
2020-03-12 19:41 ` [PATCH v6 17/42] target/arm: Restrict the values of DCZID.BS under TCG Richard Henderson
2020-03-12 19:41 ` [PATCH v6 18/42] target/arm: Simplify DC_ZVA Richard Henderson
2020-03-12 19:41 ` [PATCH v6 19/42] target/arm: Implement the LDGM, STGM, STZGM instructions Richard Henderson
2020-03-12 19:41 ` [PATCH v6 20/42] target/arm: Implement the access tag cache flushes Richard Henderson
2020-03-12 19:41 ` [PATCH v6 21/42] target/arm: Move regime_el to internals.h Richard Henderson
2020-03-12 19:41 ` [PATCH v6 22/42] target/arm: Move regime_tcr " Richard Henderson
2020-03-12 19:42 ` [PATCH v6 23/42] target/arm: Add gen_mte_check1 Richard Henderson
2020-03-12 19:42 ` [PATCH v6 24/42] target/arm: Add gen_mte_checkN Richard Henderson
2020-03-12 19:42 ` [PATCH v6 25/42] target/arm: Implement helper_mte_check1 Richard Henderson
2020-03-12 19:42 ` [PATCH v6 26/42] target/arm: Implement helper_mte_checkN Richard Henderson
2020-03-12 19:42 ` [PATCH v6 27/42] target/arm: Add helper_mte_check_zva Richard Henderson
2020-03-12 19:42 ` [PATCH v6 28/42] target/arm: Use mte_checkN for sve unpredicated loads Richard Henderson
2020-03-12 19:42 ` [PATCH v6 29/42] target/arm: Use mte_checkN for sve unpredicated stores Richard Henderson
2020-03-12 19:42 ` [PATCH v6 30/42] target/arm: Use mte_check1 for sve LD1R Richard Henderson
2020-03-12 19:42 ` [PATCH v6 31/42] target/arm: Add mte helpers for sve scalar + int loads Richard Henderson
2020-03-12 19:42 ` [PATCH v6 32/42] target/arm: Add mte helpers for sve scalar + int stores Richard Henderson
2020-03-12 19:42 ` [PATCH v6 33/42] target/arm: Add mte helpers for sve scalar + int ff/nf loads Richard Henderson
2020-03-12 19:42 ` [PATCH v6 34/42] target/arm: Handle TBI for sve scalar + int memory ops Richard Henderson
2020-03-12 19:42 ` [PATCH v6 35/42] target/arm: Add mte helpers for sve scatter/gather " Richard Henderson
2020-03-12 19:42 ` [PATCH v6 36/42] target/arm: Complete TBI clearing for user-only for SVE Richard Henderson
2020-03-12 19:42 ` [PATCH v6 37/42] target/arm: Implement data cache set allocation tags Richard Henderson
2020-03-12 19:42 ` [PATCH v6 38/42] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2020-03-12 19:42 ` [PATCH v6 39/42] target/arm: Enable MTE Richard Henderson
2020-03-12 19:42 ` [PATCH v6 40/42] target/arm: Cache the Tagged bit for a page in MemTxAttrs Richard Henderson
2020-03-12 19:42 ` [PATCH v6 41/42] target/arm: Create tagged ram when MTE is enabled Richard Henderson
2020-03-12 19:42 ` [PATCH v6 42/42] target/arm: Add allocation tag storage for system mode Richard Henderson
2020-05-18 14:46 ` [PATCH v6 00/42] target/arm: Implement ARMv8.5-MemTag, " Peter Maydell
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