From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Yoshinori Sato" <ysato@users.sourceforge.jp>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <rth@twiddle.net>
Subject: [PATCH 02/13] MAINTAINERS: Cover Renesas RX architecture
Date: Sun, 15 Mar 2020 14:27:58 +0100 [thread overview]
Message-ID: <20200315132810.7022-3-f4bug@amsat.org> (raw)
In-Reply-To: <20200315132810.7022-1-f4bug@amsat.org>
From: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200224141923.82118-2-ysato@users.sourceforge.jp>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 32867bc636..3463533aee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -276,6 +276,11 @@ F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
+RENESAS RX CPUs
+M: Yoshinori Sato <ysato@users.sourceforge.jp>
+S: Maintained
+F: target/rx/
+
S390 TCG CPUs
M: Richard Henderson <rth@twiddle.net>
M: David Hildenbrand <david@redhat.com>
--
2.21.1
next prev parent reply other threads:[~2020-03-15 13:30 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-15 13:27 [PATCH 00/13] target: Add Renesas RX architecture Philippe Mathieu-Daudé
2020-03-15 13:27 ` [PATCH 01/13] hw/registerfields.h: Add 8bit and 16bit register macros Philippe Mathieu-Daudé
2020-03-15 13:27 ` Philippe Mathieu-Daudé [this message]
2020-03-15 13:27 ` [PATCH 03/13] target/rx: TCG translation Philippe Mathieu-Daudé
2020-03-15 13:28 ` [PATCH 04/13] target/rx: TCG helpers Philippe Mathieu-Daudé
2020-03-15 13:28 ` [PATCH 05/13] target/rx: CPU definitions Philippe Mathieu-Daudé
2020-03-15 15:42 ` Philippe Mathieu-Daudé
2020-03-16 5:28 ` Yoshinori Sato
2020-03-15 22:48 ` Richard Henderson
2020-03-15 13:28 ` [PATCH 06/13] target/rx: RX disassembler Philippe Mathieu-Daudé
2020-03-15 13:28 ` [PATCH 07/13] target/rx: Disassemble rx_index_addr into a string Philippe Mathieu-Daudé
2020-03-15 13:28 ` [PATCH 08/13] target/rx: Replace operand with prt_ldmi in disassembler Philippe Mathieu-Daudé
2020-03-15 13:28 ` [PATCH 09/13] target/rx: Use prt_ldmi for XCHG_mr disassembly Philippe Mathieu-Daudé
2020-03-15 13:28 ` [PATCH 10/13] target/rx: Emit all disassembly in one prt() Philippe Mathieu-Daudé
2020-03-15 13:28 ` [PATCH 11/13] target/rx: Collect all bytes during disassembly Philippe Mathieu-Daudé
2020-03-15 13:28 ` [PATCH 12/13] target/rx: Dump bytes for each insn " Philippe Mathieu-Daudé
2020-03-15 13:28 ` [PATCH 13/13] Add rx-softmmu Philippe Mathieu-Daudé
2020-03-15 14:34 ` [PATCH 00/13] target: Add Renesas RX architecture no-reply
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