From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: lvivier@redhat.com, aik@ozlabs.ru, mdroth@linux.vnet.ibm.com,
qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org,
clg@kaod.org, "Philippe Mathieu-Daudé" <philmd@redhat.com>,
"David Gibson" <david@gibson.dropbear.id.au>
Subject: [PULL 12/45] target/ppc: Use class fields to simplify LPCR masking
Date: Tue, 17 Mar 2020 21:03:50 +1100 [thread overview]
Message-ID: <20200317100423.622643-13-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20200317100423.622643-1-david@gibson.dropbear.id.au>
When we store the Logical Partitioning Control Register (LPCR) we have a
big switch statement to work out which are valid bits for the cpu model
we're emulating.
As well as being ugly, this isn't really conceptually correct, since it is
based on the mmu_model variable, whereas the LPCR isn't (only) about the
MMU, so mmu_model is basically just acting as a proxy for the cpu model.
Handle this in a simpler way, by adding a suitable lpcr_mask to the QOM
class.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/ppc/cpu-qom.h | 1 +
target/ppc/mmu-hash64.c | 36 ++-------------------------------
target/ppc/translate_init.inc.c | 36 ++++++++++++++++++++++++++++-----
3 files changed, 34 insertions(+), 39 deletions(-)
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index e499575dc8..15d6b54a7d 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -177,6 +177,7 @@ typedef struct PowerPCCPUClass {
uint64_t insns_flags;
uint64_t insns_flags2;
uint64_t msr_mask;
+ uint64_t lpcr_mask; /* Available bits in the LPCR */
uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
powerpc_mmu_t mmu_model;
powerpc_excp_t excp_model;
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index caf47ad6fc..0ef330a614 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1095,42 +1095,10 @@ static void ppc_hash64_update_vrma(PowerPCCPU *cpu)
void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
- uint64_t lpcr = 0;
- /* Filter out bits */
- switch (env->mmu_model) {
- case POWERPC_MMU_2_03: /* P5p */
- lpcr = val & (LPCR_RMLS | LPCR_ILE |
- LPCR_LPES0 | LPCR_LPES1 |
- LPCR_RMI | LPCR_HDICE);
- break;
- case POWERPC_MMU_2_06: /* P7 */
- lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
- LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
- LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
- LPCR_MER | LPCR_TC |
- LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE);
- break;
- case POWERPC_MMU_2_07: /* P8 */
- lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
- LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
- LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
- LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
- LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
- break;
- case POWERPC_MMU_3_00: /* P9 */
- lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
- (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
- LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
- (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
- LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
- LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
- break;
- default:
- g_assert_not_reached();
- }
- env->spr[SPR_LPCR] = lpcr;
+ env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
ppc_hash64_update_rmls(cpu);
ppc_hash64_update_vrma(cpu);
}
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index f7acd3d61d..0ae145e18d 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8476,6 +8476,8 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
(1ull << MSR_DR) |
(1ull << MSR_PMM) |
(1ull << MSR_RI);
+ pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
+ LPCR_RMI | LPCR_HDICE;
pcc->mmu_model = POWERPC_MMU_2_03;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -8614,6 +8616,12 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
+ LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
+ LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
+ LPCR_MER | LPCR_TC |
+ LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -8630,7 +8638,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
- pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
}
static void init_proc_POWER8(CPUPPCState *env)
@@ -8785,6 +8792,13 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
(1ull << MSR_TS0) |
(1ull << MSR_TS1) |
(1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
+ LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
+ LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
+ LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
+ LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
+ LPCR_P8_PECE3 | LPCR_P8_PECE4;
pcc->mmu_model = POWERPC_MMU_2_07;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -8802,8 +8816,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
- pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
- LPCR_P8_PECE3 | LPCR_P8_PECE4;
}
#ifdef CONFIG_SOFTMMU
@@ -8995,6 +9007,14 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
+ (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+ LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
+ (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
+ LPCR_DEE | LPCR_OEE))
+ | LPCR_MER | LPCR_GTSE | LPCR_TC |
+ LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
pcc->mmu_model = POWERPC_MMU_3_00;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
@@ -9014,7 +9034,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
- pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
}
#ifdef CONFIG_SOFTMMU
@@ -9205,6 +9224,14 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
(1ull << MSR_PMM) |
(1ull << MSR_RI) |
(1ull << MSR_LE);
+ pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
+ (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+ LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
+ (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
+ LPCR_DEE | LPCR_OEE))
+ | LPCR_MER | LPCR_GTSE | LPCR_TC |
+ LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
+ pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
pcc->mmu_model = POWERPC_MMU_3_00;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
@@ -9223,7 +9250,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
- pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
}
#if !defined(CONFIG_USER_ONLY)
--
2.24.1
next prev parent reply other threads:[~2020-03-17 10:08 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-17 10:03 [PULL 00/45] ppc-for-5.0 queue 20200317 David Gibson
2020-03-17 10:03 ` [PULL 01/45] pseries: Update SLOF firmware image David Gibson
2020-03-17 10:03 ` [PULL 02/45] spapr: Handle pending hot plug/unplug requests at CAS David Gibson
2020-03-17 10:03 ` [PULL 03/45] ppc: Officially deprecate the CPU "compat" property David Gibson
2020-03-17 10:03 ` [PULL 04/45] spapr: Fix Coverity warning while validating nvdimm options David Gibson
2020-03-17 10:03 ` [PULL 05/45] hw/ppc/pnv: Fix typo in comment David Gibson
2020-03-17 10:03 ` [PULL 06/45] ppc: Remove stub support for 32-bit hypervisor mode David Gibson
2020-03-17 10:03 ` [PULL 07/45] ppc: Remove stub of PPC970 HID4 implementation David Gibson
2020-03-17 10:03 ` [PULL 08/45] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU David Gibson
2020-03-17 10:03 ` [PULL 09/45] target/ppc: Introduce ppc_hash64_use_vrma() helper David Gibson
2020-03-17 10:03 ` [PULL 10/45] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 David Gibson
2020-03-17 10:03 ` [PULL 11/45] target/ppc: Remove RMOR register from POWER9 & POWER10 David Gibson
2020-03-17 10:03 ` David Gibson [this message]
2020-03-17 10:03 ` [PULL 13/45] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] David Gibson
2020-03-17 10:03 ` [PULL 14/45] target/ppc: Correct RMLS table David Gibson
2020-03-17 10:03 ` [PULL 15/45] target/ppc: Only calculate RMLS derived RMA limit on demand David Gibson
2020-03-17 10:03 ` [PULL 16/45] target/ppc: Don't store VRMA SLBE persistently David Gibson
2020-03-17 10:03 ` [PULL 17/45] spapr: Don't use weird units for MIN_RMA_SLOF David Gibson
2020-03-17 10:03 ` [PULL 18/45] spapr,ppc: Simplify signature of kvmppc_rma_size() David Gibson
2020-03-17 10:03 ` [PULL 19/45] spapr: Don't attempt to clamp RMA to VRMA constraint David Gibson
2020-03-17 10:03 ` [PULL 20/45] spapr: Don't clamp RMA to 16GiB on new machine types David Gibson
2020-03-17 10:03 ` [PULL 21/45] spapr: Clean up RMA size calculation David Gibson
2020-03-17 10:04 ` [PULL 22/45] hw/scsi/viosrp: Add missing 'hw/scsi/srp.h' include David Gibson
2020-03-17 10:04 ` [PULL 23/45] hw/scsi/spapr_vscsi: Use SRP_MAX_IU_LEN instead of sizeof flexible array David Gibson
2020-03-17 10:04 ` [PULL 24/45] hw/scsi/spapr_vscsi: Simplify a bit David Gibson
2020-03-17 10:04 ` [PULL 25/45] hw/scsi/spapr_vscsi: Introduce req_iu() helper David Gibson
2020-03-17 10:04 ` [PULL 26/45] hw/scsi/spapr_vscsi: Do not mix SRP IU size with DMA buffer size David Gibson
2020-03-17 10:04 ` [PULL 27/45] hw/scsi/spapr_vscsi: Prevent buffer overflow David Gibson
2020-03-17 10:04 ` [PULL 28/45] hw/scsi/spapr_vscsi: Convert debug fprintf() to trace event David Gibson
2020-03-17 10:04 ` [PULL 29/45] spapr/xive: use SPAPR_IRQ_IPI to define IPI ranges exposed to the guest David Gibson
2020-03-17 10:04 ` [PULL 30/45] target/ppc: Fix rlwinm on ppc64 David Gibson
2020-03-17 10:04 ` [PULL 31/45] ppc/spapr: Move GPRs setup to one place David Gibson
2020-03-17 10:04 ` [PULL 32/45] pseries: Update SLOF firmware image David Gibson
2020-03-17 10:04 ` [PULL 33/45] spapr/rtas: Reserve space for RTAS blob and log David Gibson
2020-03-17 10:04 ` [PULL 34/45] spapr: Move creation of ibm, dynamic-reconfiguration-memory dt node David Gibson
2020-03-17 10:04 ` [PULL 35/45] spapr: Move creation of ibm,architecture-vec-5 property David Gibson
2020-03-17 10:04 ` [PULL 36/45] spapr: Rename DT functions to newer naming convention David Gibson
2020-03-17 10:04 ` [PULL 37/45] ppc/spapr: Fix FWNMI machine check failure handling David Gibson
2020-03-17 10:04 ` [PULL 38/45] ppc/spapr: Change FWNMI names David Gibson
2020-03-17 10:04 ` [PULL 39/45] ppc/spapr: Add FWNMI System Reset state David Gibson
2020-03-17 10:04 ` [PULL 40/45] ppc/spapr: Fix FWNMI machine check interrupt delivery David Gibson
2020-03-17 10:04 ` [PULL 41/45] ppc/spapr: Allow FWNMI on TCG David Gibson
2020-03-17 10:04 ` [PULL 42/45] target/ppc: allow ppc_cpu_do_system_reset to take an alternate vector David Gibson
2020-03-17 10:04 ` [PULL 43/45] ppc/spapr: Implement FWNMI System Reset delivery David Gibson
2020-03-17 10:04 ` [PULL 44/45] ppc/spapr: Ignore common "ibm,nmi-interlock" Linux bug David Gibson
2020-03-17 10:04 ` [PULL 45/45] pseries: Update SLOF firmware image David Gibson
2020-03-17 10:30 ` [PULL 00/45] ppc-for-5.0 queue 20200317 Paolo Bonzini
2020-03-17 22:33 ` David Gibson
2020-03-17 23:58 ` Alexey Kardashevskiy
2020-03-18 5:46 ` David Gibson
2020-03-17 11:24 ` no-reply
2020-03-18 17:57 ` Peter Maydell
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