From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: lvivier@redhat.com, aik@ozlabs.ru, mdroth@linux.vnet.ibm.com,
qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org,
clg@kaod.org, "Philippe Mathieu-Daudé" <philmd@redhat.com>,
"David Gibson" <david@gibson.dropbear.id.au>
Subject: [PULL 16/45] target/ppc: Don't store VRMA SLBE persistently
Date: Tue, 17 Mar 2020 21:03:54 +1100 [thread overview]
Message-ID: <20200317100423.622643-17-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20200317100423.622643-1-david@gibson.dropbear.id.au>
Currently, we construct the SLBE used for VRMA translations when the LPCR
is written (which controls some bits in the SLBE), then use it later for
translations.
This is a bit complex and confusing - simplify it by simply constructing
the SLBE directly from the LPCR when we need it.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/ppc/cpu.h | 3 --
target/ppc/mmu-hash64.c | 92 ++++++++++++++++-------------------------
2 files changed, 35 insertions(+), 60 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f9871b1233..5a55fb02bd 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1044,9 +1044,6 @@ struct CPUPPCState {
uint32_t flags;
uint64_t insns_flags;
uint64_t insns_flags2;
-#if defined(TARGET_PPC64)
- ppc_slb_t vrma_slb;
-#endif
int error_code;
uint32_t pending_interrupts;
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 4fd7b7ee74..34f6009b1e 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -784,11 +784,41 @@ static target_ulong rmls_limit(PowerPCCPU *cpu)
return rma_sizes[rmls];
}
+static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb)
+{
+ CPUPPCState *env = &cpu->env;
+ target_ulong lpcr = env->spr[SPR_LPCR];
+ uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
+ target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MASK);
+ int i;
+
+ for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
+ const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i];
+
+ if (!sps->page_shift) {
+ break;
+ }
+
+ if ((vsid & SLB_VSID_LLP_MASK) == sps->slb_enc) {
+ slb->esid = SLB_ESID_V;
+ slb->vsid = vsid;
+ slb->sps = sps;
+ return 0;
+ }
+ }
+
+ error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x"
+ TARGET_FMT_lx"\n", lpcr);
+
+ return -1;
+}
+
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
int rwx, int mmu_idx)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
+ ppc_slb_t vrma_slbe;
ppc_slb_t *slb;
unsigned apshift;
hwaddr ptex;
@@ -827,8 +857,8 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
}
} else if (ppc_hash64_use_vrma(env)) {
/* Emulated VRMA mode */
- slb = &env->vrma_slb;
- if (!slb->sps) {
+ slb = &vrma_slbe;
+ if (build_vrma_slbe(cpu, slb) != 0) {
/* Invalid VRMA setup, machine check */
cs->exception_index = POWERPC_EXCP_MCHECK;
env->error_code = 0;
@@ -976,6 +1006,7 @@ skip_slb_search:
hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
{
CPUPPCState *env = &cpu->env;
+ ppc_slb_t vrma_slbe;
ppc_slb_t *slb;
hwaddr ptex, raddr;
ppc_hash_pte64_t pte;
@@ -997,8 +1028,8 @@ hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr)
return raddr | env->spr[SPR_HRMOR];
} else if (ppc_hash64_use_vrma(env)) {
/* Emulated VRMA mode */
- slb = &env->vrma_slb;
- if (!slb->sps) {
+ slb = &vrma_slbe;
+ if (build_vrma_slbe(cpu, slb) != 0) {
return -1;
}
} else {
@@ -1037,65 +1068,12 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
}
-static void ppc_hash64_update_vrma(PowerPCCPU *cpu)
-{
- CPUPPCState *env = &cpu->env;
- const PPCHash64SegmentPageSizes *sps = NULL;
- target_ulong esid, vsid, lpcr;
- ppc_slb_t *slb = &env->vrma_slb;
- uint32_t vrmasd;
- int i;
-
- /* First clear it */
- slb->esid = slb->vsid = 0;
- slb->sps = NULL;
-
- /* Is VRMA enabled ? */
- if (!ppc_hash64_use_vrma(env)) {
- return;
- }
-
- /*
- * Make one up. Mostly ignore the ESID which will not be needed
- * for translation
- */
- lpcr = env->spr[SPR_LPCR];
- vsid = SLB_VSID_VRMA;
- vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT;
- vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP);
- esid = SLB_ESID_V;
-
- for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
- const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i];
-
- if (!sps1->page_shift) {
- break;
- }
-
- if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) {
- sps = sps1;
- break;
- }
- }
-
- if (!sps) {
- error_report("Bad page size encoding esid 0x"TARGET_FMT_lx
- " vsid 0x"TARGET_FMT_lx, esid, vsid);
- return;
- }
-
- slb->vsid = vsid;
- slb->esid = esid;
- slb->sps = sps;
-}
-
void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
{
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
CPUPPCState *env = &cpu->env;
env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
- ppc_hash64_update_vrma(cpu);
}
void helper_store_lpcr(CPUPPCState *env, target_ulong val)
--
2.24.1
next prev parent reply other threads:[~2020-03-17 10:16 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-17 10:03 [PULL 00/45] ppc-for-5.0 queue 20200317 David Gibson
2020-03-17 10:03 ` [PULL 01/45] pseries: Update SLOF firmware image David Gibson
2020-03-17 10:03 ` [PULL 02/45] spapr: Handle pending hot plug/unplug requests at CAS David Gibson
2020-03-17 10:03 ` [PULL 03/45] ppc: Officially deprecate the CPU "compat" property David Gibson
2020-03-17 10:03 ` [PULL 04/45] spapr: Fix Coverity warning while validating nvdimm options David Gibson
2020-03-17 10:03 ` [PULL 05/45] hw/ppc/pnv: Fix typo in comment David Gibson
2020-03-17 10:03 ` [PULL 06/45] ppc: Remove stub support for 32-bit hypervisor mode David Gibson
2020-03-17 10:03 ` [PULL 07/45] ppc: Remove stub of PPC970 HID4 implementation David Gibson
2020-03-17 10:03 ` [PULL 08/45] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU David Gibson
2020-03-17 10:03 ` [PULL 09/45] target/ppc: Introduce ppc_hash64_use_vrma() helper David Gibson
2020-03-17 10:03 ` [PULL 10/45] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 David Gibson
2020-03-17 10:03 ` [PULL 11/45] target/ppc: Remove RMOR register from POWER9 & POWER10 David Gibson
2020-03-17 10:03 ` [PULL 12/45] target/ppc: Use class fields to simplify LPCR masking David Gibson
2020-03-17 10:03 ` [PULL 13/45] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] David Gibson
2020-03-17 10:03 ` [PULL 14/45] target/ppc: Correct RMLS table David Gibson
2020-03-17 10:03 ` [PULL 15/45] target/ppc: Only calculate RMLS derived RMA limit on demand David Gibson
2020-03-17 10:03 ` David Gibson [this message]
2020-03-17 10:03 ` [PULL 17/45] spapr: Don't use weird units for MIN_RMA_SLOF David Gibson
2020-03-17 10:03 ` [PULL 18/45] spapr,ppc: Simplify signature of kvmppc_rma_size() David Gibson
2020-03-17 10:03 ` [PULL 19/45] spapr: Don't attempt to clamp RMA to VRMA constraint David Gibson
2020-03-17 10:03 ` [PULL 20/45] spapr: Don't clamp RMA to 16GiB on new machine types David Gibson
2020-03-17 10:03 ` [PULL 21/45] spapr: Clean up RMA size calculation David Gibson
2020-03-17 10:04 ` [PULL 22/45] hw/scsi/viosrp: Add missing 'hw/scsi/srp.h' include David Gibson
2020-03-17 10:04 ` [PULL 23/45] hw/scsi/spapr_vscsi: Use SRP_MAX_IU_LEN instead of sizeof flexible array David Gibson
2020-03-17 10:04 ` [PULL 24/45] hw/scsi/spapr_vscsi: Simplify a bit David Gibson
2020-03-17 10:04 ` [PULL 25/45] hw/scsi/spapr_vscsi: Introduce req_iu() helper David Gibson
2020-03-17 10:04 ` [PULL 26/45] hw/scsi/spapr_vscsi: Do not mix SRP IU size with DMA buffer size David Gibson
2020-03-17 10:04 ` [PULL 27/45] hw/scsi/spapr_vscsi: Prevent buffer overflow David Gibson
2020-03-17 10:04 ` [PULL 28/45] hw/scsi/spapr_vscsi: Convert debug fprintf() to trace event David Gibson
2020-03-17 10:04 ` [PULL 29/45] spapr/xive: use SPAPR_IRQ_IPI to define IPI ranges exposed to the guest David Gibson
2020-03-17 10:04 ` [PULL 30/45] target/ppc: Fix rlwinm on ppc64 David Gibson
2020-03-17 10:04 ` [PULL 31/45] ppc/spapr: Move GPRs setup to one place David Gibson
2020-03-17 10:04 ` [PULL 32/45] pseries: Update SLOF firmware image David Gibson
2020-03-17 10:04 ` [PULL 33/45] spapr/rtas: Reserve space for RTAS blob and log David Gibson
2020-03-17 10:04 ` [PULL 34/45] spapr: Move creation of ibm, dynamic-reconfiguration-memory dt node David Gibson
2020-03-17 10:04 ` [PULL 35/45] spapr: Move creation of ibm,architecture-vec-5 property David Gibson
2020-03-17 10:04 ` [PULL 36/45] spapr: Rename DT functions to newer naming convention David Gibson
2020-03-17 10:04 ` [PULL 37/45] ppc/spapr: Fix FWNMI machine check failure handling David Gibson
2020-03-17 10:04 ` [PULL 38/45] ppc/spapr: Change FWNMI names David Gibson
2020-03-17 10:04 ` [PULL 39/45] ppc/spapr: Add FWNMI System Reset state David Gibson
2020-03-17 10:04 ` [PULL 40/45] ppc/spapr: Fix FWNMI machine check interrupt delivery David Gibson
2020-03-17 10:04 ` [PULL 41/45] ppc/spapr: Allow FWNMI on TCG David Gibson
2020-03-17 10:04 ` [PULL 42/45] target/ppc: allow ppc_cpu_do_system_reset to take an alternate vector David Gibson
2020-03-17 10:04 ` [PULL 43/45] ppc/spapr: Implement FWNMI System Reset delivery David Gibson
2020-03-17 10:04 ` [PULL 44/45] ppc/spapr: Ignore common "ibm,nmi-interlock" Linux bug David Gibson
2020-03-17 10:04 ` [PULL 45/45] pseries: Update SLOF firmware image David Gibson
2020-03-17 10:30 ` [PULL 00/45] ppc-for-5.0 queue 20200317 Paolo Bonzini
2020-03-17 22:33 ` David Gibson
2020-03-17 23:58 ` Alexey Kardashevskiy
2020-03-18 5:46 ` David Gibson
2020-03-17 11:24 ` no-reply
2020-03-18 17:57 ` Peter Maydell
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