From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Yoshinori Sato" <ysato@users.sourceforge.jp>,
"Richard Henderson" <rth@twiddle.net>
Subject: [PULL 02/13] MAINTAINERS: Add entry for the Renesas RX architecture
Date: Tue, 17 Mar 2020 17:36:05 +0100 [thread overview]
Message-ID: <20200317163616.30027-3-f4bug@amsat.org> (raw)
In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org>
From: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200224141923.82118-2-ysato@users.sourceforge.jp>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
MAINTAINERS | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 32867bc636..3463533aee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -276,6 +276,11 @@ F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
+RENESAS RX CPUs
+M: Yoshinori Sato <ysato@users.sourceforge.jp>
+S: Maintained
+F: target/rx/
+
S390 TCG CPUs
M: Richard Henderson <rth@twiddle.net>
M: David Hildenbrand <david@redhat.com>
--
2.21.1
next prev parent reply other threads:[~2020-03-17 16:50 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-17 16:36 [PULL 00/13] target: Add the Renesas RX architecture Philippe Mathieu-Daudé
2020-03-17 16:36 ` [PULL 01/13] hw/registerfields.h: Add 8bit and 16bit register macros Philippe Mathieu-Daudé
2020-03-17 16:36 ` Philippe Mathieu-Daudé [this message]
2020-03-17 16:36 ` [PULL 03/13] target/rx: TCG translation Philippe Mathieu-Daudé
2020-04-03 16:41 ` Peter Maydell
2020-04-03 16:47 ` Richard Henderson
2020-03-17 16:36 ` [PULL 04/13] target/rx: TCG helpers Philippe Mathieu-Daudé
2021-12-09 16:04 ` Peter Maydell
2021-12-15 12:42 ` Philippe Mathieu-Daudé
2020-03-17 16:36 ` [PULL 05/13] target/rx: CPU definitions Philippe Mathieu-Daudé
2020-03-17 16:36 ` [PULL 06/13] target/rx: RX disassembler Philippe Mathieu-Daudé
2020-03-17 16:36 ` [PULL 07/13] target/rx: Disassemble rx_index_addr into a string Philippe Mathieu-Daudé
2020-03-17 16:36 ` [PULL 08/13] target/rx: Replace operand with prt_ldmi in disassembler Philippe Mathieu-Daudé
2020-03-17 16:36 ` [PULL 09/13] target/rx: Use prt_ldmi for XCHG_mr disassembly Philippe Mathieu-Daudé
2020-03-17 16:36 ` [PULL 10/13] target/rx: Emit all disassembly in one prt() Philippe Mathieu-Daudé
2020-03-17 16:36 ` [PULL 11/13] target/rx: Collect all bytes during disassembly Philippe Mathieu-Daudé
2020-03-17 16:36 ` [PULL 12/13] target/rx: Dump bytes for each insn " Philippe Mathieu-Daudé
2020-03-17 16:36 ` [PULL 13/13] Add rx-softmmu Philippe Mathieu-Daudé
2020-03-17 20:15 ` [PULL 00/13] target: Add the Renesas RX architecture no-reply
2020-03-18 1:10 ` no-reply
2020-03-18 8:20 ` Philippe Mathieu-Daudé
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