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From: Eduardo Habkost <ehabkost@redhat.com>
To: qemu-devel@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	"Moger, Babu" <Babu.Moger@amd.com>,
	Eduardo Habkost <ehabkost@redhat.com>,
	Richard Henderson <rth@twiddle.net>
Subject: [PULL 03/13] i386: Add missing cpu feature bits in EPYC model
Date: Tue, 17 Mar 2020 21:17:38 -0400	[thread overview]
Message-ID: <20200318011748.2104336-4-ehabkost@redhat.com> (raw)
In-Reply-To: <20200318011748.2104336-1-ehabkost@redhat.com>

From: "Moger, Babu" <Babu.Moger@amd.com>

Adds the following missing CPUID bits:
perfctr-core : core performance counter extensions support. Enables the VM
               to use extended performance counter support. It enables six
               programmable counters instead of 4 counters.
clzero       : instruction zeroes out the 64 byte cache line specified in RAX.
xsaveerptr   : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
               pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
               pointers.
ibpb         : Indirect Branch Prediction Barrie.
xsaves       : XSAVES, XRSTORS and IA32_XSS supported.

Depends on following kernel commits:
40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
52297436199d ("kvm: svm: Update svm_xsaves_supported")

These new features will be added in EPYC-v3. The -cpu help output after the change.
x86 EPYC-v1               AMD EPYC Processor
x86 EPYC-v2               AMD EPYC Processor (with IBPB)
x86 EPYC-v3               AMD EPYC Processor

Signed-off-by: Babu Moger <babu.moger@amd.com>
Message-Id: <157314965662.23828.3063243729449408327.stgit@naples-babu.amd.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
 target/i386/cpu.c | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index dc78494167..54f42dcd25 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3942,10 +3942,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
             CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
             CPUID_7_0_EBX_SHA_NI,
-        /* Missing: XSAVES (not supported by some Linux versions,
-         * including v4.1 to v4.12).
-         * KVM doesn't yet expose any XSAVES state save component.
-         */
         .features[FEAT_XSAVE] =
             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
             CPUID_XSAVE_XGETBV1,
@@ -3968,6 +3964,19 @@ static X86CPUDefinition builtin_x86_defs[] = {
                     { /* end of list */ }
                 }
             },
+            {
+                .version = 3,
+                .props = (PropValue[]) {
+                    { "ibpb", "on" },
+                    { "perfctr-core", "on" },
+                    { "clzero", "on" },
+                    { "xsaveerptr", "on" },
+                    { "xsaves", "on" },
+                    { "model-id",
+                      "AMD EPYC Processor" },
+                    { /* end of list */ }
+                }
+            },
             { /* end of list */ }
         }
     },
-- 
2.24.1



  parent reply	other threads:[~2020-03-18  1:19 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-18  1:17 [PULL 00/13] x86 and machine queue for 5.0 soft freeze Eduardo Habkost
2020-03-18  1:17 ` [PULL 01/13] target/i386: Add Denverton-v2 (no MPX) CPU model Eduardo Habkost
2020-03-18  1:17 ` [PULL 02/13] target/i386: Add new property note to versioned CPU models Eduardo Habkost
2020-03-18  1:17 ` Eduardo Habkost [this message]
2020-03-18  1:17 ` [PULL 04/13] i386: Add 2nd Generation AMD EPYC processors Eduardo Habkost
2020-03-18  1:17 ` [PULL 05/13] hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs Eduardo Habkost
2020-03-18  1:17 ` [PULL 06/13] machine/memory encryption: Disable mem merge Eduardo Habkost
2020-03-18  1:17 ` [PULL 07/13] cpu: Use DeviceClass reset instead of a special CPUClass reset Eduardo Habkost
2020-03-18  7:59   ` Philippe Mathieu-Daudé
2020-03-18  1:17 ` [PULL 08/13] hw/i386: Introduce X86CPUTopoInfo to contain topology info Eduardo Habkost
2020-03-18  1:17 ` [PULL 09/13] hw/i386: Consolidate topology functions Eduardo Habkost
2020-03-18  1:17 ` [PULL 10/13] machine: Add SMP Sockets in CpuTopology Eduardo Habkost
2020-03-18  1:17 ` [PULL 11/13] hw/i386: Remove unnecessary initialization in x86_cpu_new Eduardo Habkost
2020-03-18  1:17 ` [PULL 12/13] hw/i386: Update structures to save the number of nodes per package Eduardo Habkost
2020-03-18  1:17 ` [PULL 13/13] hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids Eduardo Habkost
2020-03-19 15:30 ` [PULL 00/13] x86 and machine queue for 5.0 soft freeze Peter Maydell

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