From: David Gibson <david@gibson.dropbear.id.au>
To: Nicholas Piggin <npiggin@gmail.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v3 1/2] target/ppc: Improve syscall exception logging
Date: Thu, 19 Mar 2020 17:22:26 +1100 [thread overview]
Message-ID: <20200319062226.GJ628315@umbus.fritz.box> (raw)
In-Reply-To: <20200317054918.199161-1-npiggin@gmail.com>
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On Tue, Mar 17, 2020 at 03:49:17PM +1000, Nicholas Piggin wrote:
> system calls (at least in Linux) use registers r3-r8 for inputs, so
> include those registers in the dump.
>
> This also adds a mode for PAPR hcalls, which have a different calling
> convention.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Applied to a newly created ppc-for-5.1 branch.
> ---
> Since v2:
> - Rebased on top of FWNMI series
>
> target/ppc/excp_helper.c | 30 ++++++++++++++++++++++++++----
> 1 file changed, 26 insertions(+), 4 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 08bc885ca6..81ee19ebae 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -57,12 +57,29 @@ static void ppc_hw_interrupt(CPUPPCState *env)
> #else /* defined(CONFIG_USER_ONLY) */
> static inline void dump_syscall(CPUPPCState *env)
> {
> - qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
> - " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
> + qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64
> + " r3=%016" PRIx64 " r4=%016" PRIx64 " r5=%016" PRIx64
> + " r6=%016" PRIx64 " r7=%016" PRIx64 " r8=%016" PRIx64
> " nip=" TARGET_FMT_lx "\n",
> ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
> ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
> - ppc_dump_gpr(env, 6), env->nip);
> + ppc_dump_gpr(env, 6), ppc_dump_gpr(env, 7),
> + ppc_dump_gpr(env, 8), env->nip);
> +}
> +
> +static inline void dump_hcall(CPUPPCState *env)
> +{
> + qemu_log_mask(CPU_LOG_INT, "hypercall r3=%016" PRIx64
> + " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
> + " r7=%016" PRIx64 " r8=%016" PRIx64 " r9=%016" PRIx64
> + " r10=%016" PRIx64 " r11=%016" PRIx64 " r12=%016" PRIx64
> + " nip=" TARGET_FMT_lx "\n",
> + ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4),
> + ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6),
> + ppc_dump_gpr(env, 7), ppc_dump_gpr(env, 8),
> + ppc_dump_gpr(env, 9), ppc_dump_gpr(env, 10),
> + ppc_dump_gpr(env, 11), ppc_dump_gpr(env, 12),
> + env->nip);
> }
>
> static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp,
> @@ -379,9 +396,14 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> }
> break;
> case POWERPC_EXCP_SYSCALL: /* System call exception */
> - dump_syscall(env);
> lev = env->error_code;
>
> + if ((lev == 1) && cpu->vhyp) {
> + dump_hcall(env);
> + } else {
> + dump_syscall(env);
> + }
> +
> /*
> * We need to correct the NIP which in this case is supposed
> * to point to the next instruction
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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prev parent reply other threads:[~2020-03-19 6:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-17 5:49 [PATCH v3 1/2] target/ppc: Improve syscall exception logging Nicholas Piggin
2020-03-17 5:49 ` [PATCH v3 2/2] target/ppc: Add support for scv and rfscv instructions Nicholas Piggin
2020-03-19 6:22 ` David Gibson
2020-03-19 6:22 ` David Gibson [this message]
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