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dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:49454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jFDNS-0000tL-4a for qemu-devel@archiver.kernel.org; Fri, 20 Mar 2020 04:51:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48096) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jFDMb-0007zP-Oj for qemu-devel@nongnu.org; Fri, 20 Mar 2020 04:50:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jFDMa-0002r4-33 for qemu-devel@nongnu.org; Fri, 20 Mar 2020 04:50:45 -0400 Received: from bilbo.ozlabs.org ([203.11.71.1]:53395 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jFDMZ-0002h0-0p; Fri, 20 Mar 2020 04:50:44 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 48kHY73bh2z9sSN; Fri, 20 Mar 2020 19:50:35 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1584694235; bh=joyYpIWAtsYaCGLoDXyLrFrtPpTupBaYcHdFyMVkTa4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Z/xhzbzDVm2SpYxEPKgONlXfU2yDS6qF9rVlpQi6r35ynAXxhnYC2U1kfy3tCMUZE st0LAJrHU5OTvvHMZ5mAUFJYt6r9ooUOzc/7TiMsKcN7DIKlGdvwjr0Zc5UpEJvOO6 NLqrOqxP/4ZzWTfZd1hOmFZoBXZtyhxVP7xV5kQI= Date: Fri, 20 Mar 2020 19:49:44 +1100 From: David Gibson To: Nicholas Piggin Subject: Re: [PATCH v2] target/ppc: Fix ISA v3.0 (POWER9) slbia implementation Message-ID: <20200320084944.GC781112@umbus.fritz.box> References: <20200319064439.1020571-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="DIOMP1UsTsWJauNi" Content-Disposition: inline In-Reply-To: <20200319064439.1020571-1-npiggin@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?iso-8859-1?Q?C=E9dric?= Le Goater , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --DIOMP1UsTsWJauNi Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Mar 19, 2020 at 04:44:39PM +1000, Nicholas Piggin wrote: > The new ISA v3.0 slbia variants have not been implemented for TCG, > which can lead to crashing when a POWER9 machine boots Linux using > the hash MMU, for example ("disable_radix" kernel command line). >=20 > Add them. >=20 > Signed-off-by: Nicholas Piggin Applied to ppc-for-5.0. > --- > Changes in v2: > - Rewrite changelog. > - Remove stray slbie hunk that crept in >=20 > I don't think the slbie invalidation is necessary, as explained on the > list. >=20 > target/ppc/helper.h | 2 +- > target/ppc/mmu-hash64.c | 56 +++++++++++++++++++++++++++++++++++------ > target/ppc/translate.c | 5 +++- > 3 files changed, 54 insertions(+), 9 deletions(-) >=20 > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index ee1498050d..2dfa1c6942 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -615,7 +615,7 @@ DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, = env, tl, tl) > DEF_HELPER_2(load_slb_esid, tl, env, tl) > DEF_HELPER_2(load_slb_vsid, tl, env, tl) > DEF_HELPER_2(find_slb_vsid, tl, env, tl) > -DEF_HELPER_FLAGS_1(slbia, TCG_CALL_NO_RWG, void, env) > +DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32) > DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl) > DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl) > #endif > diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c > index 373d44de74..e5baabf0e1 100644 > --- a/target/ppc/mmu-hash64.c > +++ b/target/ppc/mmu-hash64.c > @@ -95,9 +95,10 @@ void dump_slb(PowerPCCPU *cpu) > } > } > =20 > -void helper_slbia(CPUPPCState *env) > +void helper_slbia(CPUPPCState *env, uint32_t ih) > { > PowerPCCPU *cpu =3D env_archcpu(env); > + int starting_entry; > int n; > =20 > /* > @@ -111,18 +112,59 @@ void helper_slbia(CPUPPCState *env) > * expected that slbmte is more common than slbia, and slbia is usua= lly > * going to evict valid SLB entries, so that tradeoff is unlikely to= be a > * good one. > + * > + * ISA v2.05 introduced IH field with values 0,1,2,6. These all inva= lidate > + * the same SLB entries (everything but entry 0), but differ in what > + * "lookaside information" is invalidated. TCG can ignore this and f= lush > + * everything. > + * > + * ISA v3.0 introduced additional values 3,4,7, which change what SL= Bs are > + * invalidated. > */ > =20 > - /* XXX: Warning: slbia never invalidates the first segment */ > - for (n =3D 1; n < cpu->hash64_opts->slb_size; n++) { > - ppc_slb_t *slb =3D &env->slb[n]; > + env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; > + > + starting_entry =3D 1; /* default for IH=3D0,1,2,6 */ > + > + if (env->mmu_model =3D=3D POWERPC_MMU_3_00) { > + switch (ih) { > + case 0x7: > + /* invalidate no SLBs, but all lookaside information */ > + return; > =20 > - if (slb->esid & SLB_ESID_V) { > - slb->esid &=3D ~SLB_ESID_V; > + case 0x3: > + case 0x4: > + /* also considers SLB entry 0 */ > + starting_entry =3D 0; > + break; > + > + case 0x5: > + /* treat undefined values as ih=3D=3D0, and warn */ > + qemu_log_mask(LOG_GUEST_ERROR, > + "slbia undefined IH field %u.\n", ih); > + break; > + > + default: > + /* 0,1,2,6 */ > + break; > } > } > =20 > - env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; > + for (n =3D starting_entry; n < cpu->hash64_opts->slb_size; n++) { > + ppc_slb_t *slb =3D &env->slb[n]; > + > + if (!(slb->esid & SLB_ESID_V)) { > + continue; > + } > + if (env->mmu_model =3D=3D POWERPC_MMU_3_00) { > + if (ih =3D=3D 0x3 && (slb->vsid & SLB_VSID_C) =3D=3D 0) { > + /* preserves entries with a class value of 0 */ > + continue; > + } > + } > + > + slb->esid &=3D ~SLB_ESID_V; > + } > } > =20 > static void __helper_slbie(CPUPPCState *env, target_ulong addr, > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index eb0ddba850..e514732a09 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -5027,12 +5027,15 @@ static void gen_tlbsync(DisasContext *ctx) > /* slbia */ > static void gen_slbia(DisasContext *ctx) > { > + uint32_t ih =3D (ctx->opcode >> 21) & 0x7; > + TCGv_i32 t0 =3D tcg_const_i32(ih); > + > #if defined(CONFIG_USER_ONLY) > GEN_PRIV; > #else > CHK_SV; > =20 > - gen_helper_slbia(cpu_env); > + gen_helper_slbia(cpu_env, t0); > #endif /* defined(CONFIG_USER_ONLY) */ > } > =20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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