From: Changbin Du <changbin.du@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
Changbin Du <changbin.du@gmail.com>
Subject: [PATCH] target/arm: fix incorrect current EL bug in aarch32 exception emulation
Date: Sat, 28 Mar 2020 22:02:32 +0800 [thread overview]
Message-ID: <20200328140232.17278-1-changbin.du@gmail.com> (raw)
The arm_current_el() should be invoked after mode switching. Otherwise, we
get a wrong current EL value, since current EL is also determined by
current mode.
Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry")
Signed-off-by: Changbin Du <changbin.du@gmail.com>
---
target/arm/helper.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b7b6887241..163c91a1cc 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9172,7 +9172,6 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
/* Change the CPU state so as to actually take the exception. */
switch_mode(env, new_mode);
- new_el = arm_current_el(env);
/*
* For exceptions taken to AArch32 we must clear the SS bit in both
@@ -9184,6 +9183,10 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode,
env->condexec_bits = 0;
/* Switch to the new mode, and to the correct instruction set. */
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
+
+ /* This must be after mode switching. */
+ new_el = arm_current_el(env);
+
/* Set new mode endianness */
env->uncached_cpsr &= ~CPSR_E;
if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {
--
2.25.1
next reply other threads:[~2020-03-28 14:03 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-28 14:02 Changbin Du [this message]
2020-03-29 3:56 ` [PATCH] target/arm: fix incorrect current EL bug in aarch32 exception emulation Richard Henderson
2020-03-30 9:09 ` Changbin Du
2020-03-30 13:07 ` Peter Maydell
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