From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: "Cédric Le Goater" <clg@kaod.org>,
qemu-ppc@nongnu.org, "Greg Kurz" <groug@kaod.org>,
qemu-devel@nongnu.org
Subject: [PATCH v2 0/2] ppc/xive: Add support for PQ state bits offload
Date: Wed, 1 Apr 2020 18:46:51 +0200 [thread overview]
Message-ID: <20200401164653.28231-1-clg@kaod.org> (raw)
Hello,
When the XIVE router unit receives a trigger message coming from a HW
source, it contains a special bit informing the XIVE interrupt
controller that the PQ bits have been checked at the source or
not. Depending on the value, the IC can perform the check and the
state transition locally using its own PQ state bits.
The following changes add new accessors to the XiveRouter required to
query and update the PQ state bits. This is only applies to the
PowerNV machine, sPAPR is not concerned by such complex configuration.
We will use it for upcoming features offloading event coalescing on
the interrupt controller.
Thanks,
C.
Cédric Le Goater (2):
ppc/xive: export PQ routines
ppc/xive: Add support for PQ state bits offload
include/hw/ppc/xive.h | 12 +++++++--
hw/intc/pnv_xive.c | 37 ++++++++++++++++++++++++---
hw/intc/spapr_xive_kvm.c | 8 +++---
hw/intc/xive.c | 54 ++++++++++++++++++++++++++++++++--------
hw/pci-host/pnv_phb4.c | 9 +++++--
hw/ppc/pnv_psi.c | 8 ++++--
6 files changed, 105 insertions(+), 23 deletions(-)
--
2.21.1
next reply other threads:[~2020-04-01 16:49 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-01 16:46 Cédric Le Goater [this message]
2020-04-01 16:46 ` [PATCH v2 1/2] ppc/xive: export PQ routines Cédric Le Goater
2020-04-01 16:46 ` [PATCH v2 2/2] ppc/xive: Add support for PQ state bits offload Cédric Le Goater
2020-04-02 10:51 ` Greg Kurz
2020-05-25 10:04 ` Cédric Le Goater
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