From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70202C43331 for ; Wed, 1 Apr 2020 18:42:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 442AB2054F for ; Wed, 1 Apr 2020 18:42:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 442AB2054F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:35890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jJiJj-000075-AI for qemu-devel@archiver.kernel.org; Wed, 01 Apr 2020 14:42:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55277) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jJiJ9-000857-Du for qemu-devel@nongnu.org; Wed, 01 Apr 2020 14:41:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jJiJ8-0004Be-BA for qemu-devel@nongnu.org; Wed, 01 Apr 2020 14:41:47 -0400 Received: from mga06.intel.com ([134.134.136.31]:41020) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jJiJ8-00045a-3z; Wed, 01 Apr 2020 14:41:46 -0400 IronPort-SDR: Xh/Sb8/XtERS8ugcg7UdlqOgESQK1c1OszWK+lQoS1ahTjzKIdf1JR4whFzZierzjTVeiv/fb9 mGfKO4klSU3Q== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Apr 2020 11:41:37 -0700 IronPort-SDR: xvyFNyhD1Xz8ISKGBcbGPD9bNwDL4zCSEzadfFRYgvgmHWgPiuQXRsXBJRAM+k+0++bKLXmtO9 GMwtDab5xTKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,332,1580803200"; d="scan'208";a="359943800" Received: from unknown (HELO localhost.ch.intel.com) ([10.2.28.117]) by fmsmga001.fm.intel.com with ESMTP; 01 Apr 2020 11:41:36 -0700 From: Andrzej Jakowski To: kbusch@kernel.org, kwolf@redhat.com, mreitz@redhat.com Subject: [PATCH v1] nvme: indicate CMB support through controller capabilities register Date: Wed, 1 Apr 2020 11:42:19 -0700 Message-Id: <20200401184219.14911-1-andrzej.jakowski@linux.intel.com> X-Mailer: git-send-email 2.21.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 134.134.136.31 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrzej Jakowski , qemu-devel@nongnu.org, qemu-block@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch sets CMBS bit in controller capabilities register when user configures NVMe driver with CMB support, so capabilites are correctly reported to guest OS. Signed-off-by: Andrzej Jakowski --- hw/block/nvme.c | 2 ++ include/block/nvme.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index d28335cbf3..986803398f 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1393,6 +1393,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error **errp) n->bar.intmc = n->bar.intms = 0; if (n->cmb_size_mb) { + /* Contoller capabilities */ + NVME_CAP_SET_CMBS(n->bar.cap, 1); NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); diff --git a/include/block/nvme.h b/include/block/nvme.h index 8fb941c653..561891b140 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -27,6 +27,7 @@ enum NvmeCapShift { CAP_CSS_SHIFT = 37, CAP_MPSMIN_SHIFT = 48, CAP_MPSMAX_SHIFT = 52, + CAP_CMB_SHIFT = 57, }; enum NvmeCapMask { @@ -39,6 +40,7 @@ enum NvmeCapMask { CAP_CSS_MASK = 0xff, CAP_MPSMIN_MASK = 0xf, CAP_MPSMAX_MASK = 0xf, + CAP_CMB_MASK = 0x1, }; #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) @@ -69,6 +71,8 @@ enum NvmeCapMask { << CAP_MPSMIN_SHIFT) #define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\ << CAP_MPSMAX_SHIFT) +#define NVME_CAP_SET_CMBS(cap, val) (cap |= (uint64_t)(val & CAP_CMB_MASK)\ + << CAP_CMB_SHIFT) enum NvmeCcShift { CC_EN_SHIFT = 0, -- 2.21.1