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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id f187sm25163765wme.9.2020.04.06.03.12.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Apr 2020 03:12:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/11] target/arm: Remove obsolete TODO note from get_phys_addr_lpae() Date: Mon, 6 Apr 2020 11:11:58 +0100 Message-Id: <20200406101205.23027-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200406101205.23027-1-peter.maydell@linaro.org> References: <20200406101205.23027-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" An old comment in get_phys_addr_lpae() claims that the code does not support the different format TCR for VTCR_EL2. This used to be true but it is not true now (in particular the aa64_va_parameters() and aa32_va_parameters() functions correctly handle the different register format by checking whether the mmu_idx is Stage2). Remove the out of date parts of the comment. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200331143407.3186-1-peter.maydell@linaro.org --- target/arm/helper.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ed7eb8ab54e..7e9ea5d20fa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10753,12 +10753,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, bool aarch64 = arm_el_is_aa64(env, el); bool guarded = false; - /* TODO: - * This code does not handle the different format TCR for VTCR_EL2. - * This code also does not support shareability levels. - * Attribute and permission bit handling should also be checked when adding - * support for those page table walks. - */ + /* TODO: This code does not support shareability levels. */ if (aarch64) { param = aa64_va_parameters(env, address, mmu_idx, access_type != MMU_INST_FETCH); -- 2.20.1