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[83.42.57.116]) by smtp.gmail.com with ESMTPSA id a67sm364880wmc.30.2020.04.06.10.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Apr 2020 10:48:11 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Markus Armbruster Subject: [PATCH-for-5.1 v2 19/54] hw/riscv/sifive_e: Move some code from realize() to init() Date: Mon, 6 Apr 2020 19:47:08 +0200 Message-Id: <20200406174743.16956-20-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200406174743.16956-1-f4bug@amsat.org> References: <20200406174743.16956-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Vladimir Sementsov-Ogievskiy , "open list:RISC-V TCG CPUs" , Sagar Karandikar , Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Coccinelle reported: $ spatch ... --timeout 60 --sp-file \ scripts/coccinelle/simplify-init-realize-error_propagate.cocci HANDLING: ./hw/riscv/sifive_e.c >>> possible moves from riscv_sifive_e_soc_init() to riscv_sifive_e_soc_realize() in ./hw/riscv/sifive_e.c:135 Move the calls using &error_fatal which don't depend of input updated before realize() to init(). Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/sifive_e.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 646553a7c3..0be8b52147 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -118,7 +118,9 @@ static void riscv_sifive_e_init(MachineState *machine) static void riscv_sifive_e_soc_init(Object *obj) { MachineState *ms = MACHINE(qdev_get_machine()); + const struct MemmapEntry *memmap = sifive_e_memmap; SiFiveESoCState *s = RISCV_E_SOC(obj); + MemoryRegion *sys_mem = get_system_memory(); object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY, @@ -130,6 +132,18 @@ static void riscv_sifive_e_soc_init(Object *obj) sysbus_init_child_obj(obj, "riscv.sifive.e.gpio0", &s->gpio, sizeof(s->gpio), TYPE_SIFIVE_GPIO); + + /* Mask ROM */ + memory_region_init_rom(&s->mask_rom, obj, "riscv.sifive.e.mrom", + memmap[SIFIVE_E_MROM].size, &error_fatal); + memory_region_add_subregion(sys_mem, + memmap[SIFIVE_E_MROM].base, &s->mask_rom); + + /* Flash memory */ + memory_region_init_rom(&s->xip_mem, obj, "riscv.sifive.e.xip", + memmap[SIFIVE_E_XIP].size, &error_fatal); + memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, + &s->xip_mem); } static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) @@ -144,12 +158,6 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) object_property_set_bool(OBJECT(&s->cpus), true, "realized", &error_abort); - /* Mask ROM */ - memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom", - memmap[SIFIVE_E_MROM].size, &error_fatal); - memory_region_add_subregion(sys_mem, - memmap[SIFIVE_E_MROM].base, &s->mask_rom); - /* MMIO */ s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base, (char *)SIFIVE_E_PLIC_HART_CONFIG, @@ -206,12 +214,6 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); create_unimplemented_device("riscv.sifive.e.pwm2", memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); - - /* Flash memory */ - memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip", - memmap[SIFIVE_E_XIP].size, &error_fatal); - memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, - &s->xip_mem); } static void riscv_sifive_e_machine_init(MachineClass *mc) -- 2.21.1