From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: victor.zhangxiaofeng@huawei.com, zhang.zhanghailiang@huawei.com,
sagark@eecs.berkeley.edu, yinyipeng1@huawei.com,
kbastian@mail.uni-paderborn.de, anup.patel@wdc.com,
Alistair.Francis@wdc.com, kvm-riscv@lists.infradead.org,
palmer@dabbelt.com, Yifei Jiang <jiangyifei@huawei.com>,
dengkai1@huawei.com
Subject: [PATCH RFC v2 3/9] target/riscv: Implement function kvm_arch_init_vcpu
Date: Sat, 11 Apr 2020 12:14:21 +0800 [thread overview]
Message-ID: <20200411041427.14828-4-jiangyifei@huawei.com> (raw)
In-Reply-To: <20200411041427.14828-1-jiangyifei@huawei.com>
Get isa info from kvm while kvm init.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/kvm.c | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 8c386d9acf..3e8f8e7185 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -38,6 +38,18 @@
#include "qemu/log.h"
#include "hw/loader.h"
+static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
+{
+ __u64 id = KVM_REG_RISCV | type | idx;
+
+#if defined(TARGET_RISCV32)
+ id |= KVM_REG_SIZE_U32;
+#elif defined(TARGET_RISCV64)
+ id |= KVM_REG_SIZE_U64;
+#endif
+ return id;
+}
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
@@ -79,7 +91,19 @@ void kvm_arch_init_irq_routing(KVMState *s)
int kvm_arch_init_vcpu(CPUState *cs)
{
- return 0;
+ int ret = 0;
+ uint64_t isa;
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ __u64 id;
+
+ id = kvm_riscv_reg_id(KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG(isa));
+ ret = kvm_get_one_reg(cs, id, &isa);
+ if (ret) {
+ return ret;
+ }
+ cpu->env.misa = isa;
+
+ return ret;
}
int kvm_arch_msi_data_to_gsi(uint32_t data)
--
2.19.1
next prev parent reply other threads:[~2020-04-11 4:17 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-11 4:14 [PATCH RFC v2 0/9] Add riscv kvm accel support Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 1/9] linux-header: Update linux/kvm.h Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2020-04-17 22:34 ` Alistair Francis
2020-04-11 4:14 ` Yifei Jiang [this message]
2020-04-11 4:14 ` [PATCH RFC v2 4/9] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 5/9] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 6/9] target/riscv: Support start kernel directly by KVM Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 9/9] target/riscv: add host cpu type Yifei Jiang
2020-04-11 5:47 ` [PATCH RFC v2 0/9] Add riscv kvm accel support no-reply
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