From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: victor.zhangxiaofeng@huawei.com, zhang.zhanghailiang@huawei.com,
sagark@eecs.berkeley.edu, yinyipeng1@huawei.com,
kbastian@mail.uni-paderborn.de, anup.patel@wdc.com,
Alistair.Francis@wdc.com, kvm-riscv@lists.infradead.org,
palmer@dabbelt.com, Yifei Jiang <jiangyifei@huawei.com>,
dengkai1@huawei.com
Subject: [PATCH RFC v2 4/9] target/riscv: Implement kvm_arch_get_registers
Date: Sat, 11 Apr 2020 12:14:22 +0800 [thread overview]
Message-ID: <20200411041427.14828-5-jiangyifei@huawei.com> (raw)
In-Reply-To: <20200411041427.14828-1-jiangyifei@huawei.com>
Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
target/riscv/kvm.c | 144 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 143 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 3e8f8e7185..8d5069b9e9 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -50,13 +50,155 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx)
return id;
}
+#define RISCV_CORE_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CORE, \
+ KVM_REG_RISCV_CORE_REG(name))
+
+#define RISCV_CSR_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CSR, \
+ KVM_REG_RISCV_CSR_REG(name))
+
+#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_F, idx)
+
+#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx)
+
+static int kvm_riscv_get_regs_core(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ uint64_t reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ ret = kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), ®);
+ if (ret) {
+ return ret;
+ }
+ env->pc = reg;
+
+ for (i = 1; i < 32; i++) {
+ __u64 id = kvm_riscv_reg_id(KVM_REG_RISCV_CORE, i);
+ ret = kvm_get_one_reg(cs, id, ®);
+ if (ret) {
+ return ret;
+ }
+ env->gpr[i] = reg;
+ }
+
+ return ret;
+}
+
+static int kvm_riscv_get_regs_csr(CPUState *cs)
+{
+ int ret = 0;
+ uint64_t reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sstatus), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mstatus = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sie), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mie = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(stvec), ®);
+ if (ret) {
+ return ret;
+ }
+ env->stvec = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sscratch), ®);
+ if (ret) {
+ return ret;
+ }
+ env->sscratch = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sepc), ®);
+ if (ret) {
+ return ret;
+ }
+ env->sepc = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(scause), ®);
+ if (ret) {
+ return ret;
+ }
+ env->scause = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sip), ®);
+ if (ret) {
+ return ret;
+ }
+ env->mip = reg;
+
+ ret = kvm_get_one_reg(cs, RISCV_CSR_REG(sstatus), ®);
+ if (ret) {
+ return ret;
+ }
+ env->satp = reg;
+
+ return ret;
+}
+
+static int kvm_riscv_get_regs_fp(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (riscv_has_ext(env, RVD)) {
+ uint64_t reg;
+ for (i = 0; i < 32; i++) {
+ ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®);
+ if (ret) {
+ return ret;
+ }
+ env->fpr[i] = reg;
+ }
+ return ret;
+ }
+
+ if (riscv_has_ext(env, RVF)) {
+ uint32_t reg;
+ for (i = 0; i < 32; i++) {
+ ret = kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®);
+ if (ret) {
+ return ret;
+ }
+ env->fpr[i] = reg;
+ }
+ return ret;
+ }
+
+ return ret;
+}
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
int kvm_arch_get_registers(CPUState *cs)
{
- return 0;
+ int ret = 0;
+
+ ret = kvm_riscv_get_regs_core(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_get_regs_csr(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_get_regs_fp(cs);
+ if (ret) {
+ return ret;
+ }
+
+ return ret;
}
int kvm_arch_put_registers(CPUState *cs, int level)
--
2.19.1
next prev parent reply other threads:[~2020-04-11 4:17 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-11 4:14 [PATCH RFC v2 0/9] Add riscv kvm accel support Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 1/9] linux-header: Update linux/kvm.h Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2020-04-17 22:34 ` Alistair Francis
2020-04-11 4:14 ` [PATCH RFC v2 3/9] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2020-04-11 4:14 ` Yifei Jiang [this message]
2020-04-11 4:14 ` [PATCH RFC v2 5/9] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 6/9] target/riscv: Support start kernel directly by KVM Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 9/9] target/riscv: add host cpu type Yifei Jiang
2020-04-11 5:47 ` [PATCH RFC v2 0/9] Add riscv kvm accel support no-reply
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