From: Yifei Jiang <jiangyifei@huawei.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: victor.zhangxiaofeng@huawei.com, zhang.zhanghailiang@huawei.com,
sagark@eecs.berkeley.edu, yinyipeng1@huawei.com,
kbastian@mail.uni-paderborn.de, anup.patel@wdc.com,
Alistair.Francis@wdc.com, kvm-riscv@lists.infradead.org,
palmer@dabbelt.com, Yifei Jiang <jiangyifei@huawei.com>,
dengkai1@huawei.com
Subject: [PATCH RFC v2 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled
Date: Sat, 11 Apr 2020 12:14:25 +0800 [thread overview]
Message-ID: <20200411041427.14828-8-jiangyifei@huawei.com> (raw)
In-Reply-To: <20200411041427.14828-1-jiangyifei@huawei.com>
Only support supervisor external interrupt currently.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
hw/riscv/sifive_plic.c | 31 ++++++++++++++++++++++---------
target/riscv/kvm.c | 19 +++++++++++++++++++
target/riscv/kvm_riscv.h | 1 +
3 files changed, 42 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index c1e04cbb98..ff5c18ed20 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -29,6 +29,8 @@
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
#include "hw/riscv/sifive_plic.h"
+#include "sysemu/kvm.h"
+#include "kvm_riscv.h"
#define RISCV_DEBUG_PLIC 0
@@ -145,15 +147,26 @@ static void sifive_plic_update(SiFivePLICState *plic)
continue;
}
int level = sifive_plic_irqs_pending(plic, addrid);
- switch (mode) {
- case PLICMode_M:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
- break;
- case PLICMode_S:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
- break;
- default:
- break;
+ if (kvm_enabled()) {
+ if (mode == PLICMode_M) {
+ continue;
+ }
+#ifdef CONFIG_KVM
+ kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level);
+#endif
+ } else {
+ switch (mode) {
+ case PLICMode_M:
+ riscv_cpu_update_mip(RISCV_CPU(cpu),
+ MIP_MEIP, BOOL_TO_MASK(level));
+ break;
+ case PLICMode_S:
+ riscv_cpu_update_mip(RISCV_CPU(cpu),
+ MIP_SEIP, BOOL_TO_MASK(level));
+ break;
+ default:
+ break;
+ }
}
}
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index b9aec66b69..0f429fd802 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -440,3 +440,22 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
env->gpr[11] = cpu->env.fdt_start; /* a1 */
}
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+ int ret;
+ unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
+
+ if (irq != IRQ_S_EXT) {
+ return;
+ }
+
+ if (!kvm_enabled()) {
+ return;
+ }
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
+ if (ret < 0) {
+ perror("Set irq failed");
+ abort();
+ }
+}
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index f38c82bf59..ed281bdce0 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -20,5 +20,6 @@
#define QEMU_KVM_RISCV_H
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
#endif
--
2.19.1
next prev parent reply other threads:[~2020-04-11 4:19 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-11 4:14 [PATCH RFC v2 0/9] Add riscv kvm accel support Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 1/9] linux-header: Update linux/kvm.h Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Yifei Jiang
2020-04-17 22:34 ` Alistair Francis
2020-04-11 4:14 ` [PATCH RFC v2 3/9] target/riscv: Implement function kvm_arch_init_vcpu Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 4/9] target/riscv: Implement kvm_arch_get_registers Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 5/9] target/riscv: Implement kvm_arch_put_registers Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 6/9] target/riscv: Support start kernel directly by KVM Yifei Jiang
2020-04-11 4:14 ` Yifei Jiang [this message]
2020-04-11 4:14 ` [PATCH RFC v2 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit Yifei Jiang
2020-04-11 4:14 ` [PATCH RFC v2 9/9] target/riscv: add host cpu type Yifei Jiang
2020-04-11 5:47 ` [PATCH RFC v2 0/9] Add riscv kvm accel support no-reply
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