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[83.42.57.116]) by smtp.gmail.com with ESMTPSA id m1sm3689226wro.64.2020.04.21.06.19.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 06:19:42 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 3/6] target/arm: Make cpu_register() available for other files Date: Tue, 21 Apr 2020 15:19:23 +0200 Message-Id: <20200421131926.12116-4-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200421131926.12116-1-philmd@redhat.com> References: <20200421131926.12116-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=UTF-8; text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=207.211.31.120; envelope-from=philmd@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/21 04:54:00 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Richard Henderson , Eric Auger , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Thomas Huth Make cpu_register() (renamed to arm_cpu_register()) available from internals.h so we can register CPUs also from other files in the future. Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-ID: <20190921150420.30743-2-thuth@redhat.com> [PMD: Split Thomas's patch in two: set_feature (earlier), cpu_register] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu-qom.h | 9 ++++++++- target/arm/cpu.c | 10 ++-------- target/arm/cpu64.c | 8 +------- 3 files changed, 11 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index d95568bf05..56395b87f6 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -35,7 +35,14 @@ struct arm_boot_info; =20 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU =20 -typedef struct ARMCPUInfo ARMCPUInfo; +typedef struct ARMCPUInfo { + const char *name; + void (*initfn)(Object *obj); + void (*class_init)(ObjectClass *oc, void *data); +} ARMCPUInfo; + +void arm_cpu_register(const ARMCPUInfo *info); +void aarch64_cpu_register(const ARMCPUInfo *info); =20 /** * ARMCPUClass: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 37f18d1648..6c84e99a38 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2683,12 +2683,6 @@ static void arm_max_initfn(Object *obj) =20 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo arm_cpus[] =3D { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) { .name =3D "arm926", .initfn =3D arm926_initfn }, @@ -2854,7 +2848,7 @@ static void cpu_register_class_init(ObjectClass *oc, = void *data) acc->info =3D data; } =20 -static void cpu_register(const ARMCPUInfo *info) +void arm_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_ARM_CPU, @@ -2895,7 +2889,7 @@ static void arm_cpu_register_types(void) type_register_static(&idau_interface_type_info); =20 while (info->name) { - cpu_register(info); + arm_cpu_register(info); info++; } =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 622082eae2..e89388378b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -728,12 +728,6 @@ static void aarch64_max_initfn(Object *obj) cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal); } =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, @@ -816,7 +810,7 @@ static void cpu_register_class_init(ObjectClass *oc, vo= id *data) acc->info =3D data; } =20 -static void aarch64_cpu_register(const ARMCPUInfo *info) +void aarch64_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_AARCH64_CPU, --=20 2.21.1