From: Anup Patel <anup.patel@wdc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atish.patra@wdc.com>,
Anup Patel <anup.patel@wdc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Anup Patel <anup@brainfault.org>
Subject: [PATCH v3 0/3] RISC-V Spike machine improvements
Date: Mon, 27 Apr 2020 13:36:41 +0530 [thread overview]
Message-ID: <20200427080644.168461-1-anup.patel@wdc.com> (raw)
This series improves QEMU Spike machine to:
1. Allow loading OpenBI firmware using -bios option
2. Allow more than one CPUs
Changes since v2:
- Rebased on QEMU v5.0-rc4
Changes since v1:
- Rebased on QEMU master (commit 2ac031d171ccd18c973014d9978b4a63f0ad5fb0)
Anup Patel (3):
hw/riscv: Add optional symbol callback ptr to riscv_load_firmware()
hw/riscv/spike: Allow loading firmware separately using -bios option
hw/riscv/spike: Allow more than one CPUs
hw/riscv/boot.c | 13 ++++++++-----
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 26 ++++++++++++++++++++++++--
hw/riscv/virt.c | 2 +-
include/hw/riscv/boot.h | 6 ++++--
5 files changed, 38 insertions(+), 11 deletions(-)
--
2.25.1
next reply other threads:[~2020-04-27 8:08 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-27 8:06 Anup Patel [this message]
2020-04-27 8:06 ` [PATCH v3 1/3] hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() Anup Patel
2020-04-27 15:05 ` Alistair Francis
2020-04-27 8:06 ` [PATCH v3 2/3] hw/riscv/spike: Allow loading firmware separately using -bios option Anup Patel
2020-04-27 15:03 ` Alistair Francis
2020-04-27 8:06 ` [PATCH v3 3/3] hw/riscv/spike: Allow more than one CPUs Anup Patel
2020-04-27 15:00 ` Alistair Francis
2020-04-27 15:05 ` [PATCH v3 0/3] RISC-V Spike machine improvements Alistair Francis
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