From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: peter.maydell@linaro.org
Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org,
qemu-devel@nongnu.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com, palmer@dabbelt.com,
alistair23@gmail.com, alex.bennee@linaro.org,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [RFC PATCH 3/8] riscv: Define riscv struct reginfo
Date: Thu, 30 Apr 2020 15:21:34 +0800 [thread overview]
Message-ID: <20200430072139.4602-4-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
risu_reginfo_riscv64.h | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 risu_reginfo_riscv64.h
diff --git a/risu_reginfo_riscv64.h b/risu_reginfo_riscv64.h
new file mode 100644
index 0000000..7d365a8
--- /dev/null
+++ b/risu_reginfo_riscv64.h
@@ -0,0 +1,29 @@
+/******************************************************************************
+ * Copyright (c) 2020 PingTouGe Semiconductor
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ * LIU Zhiwei(PingTouGe) - initial implementation
+ * based on Peter Maydell's risu_arm.c
+ *****************************************************************************/
+
+#ifndef RISU_REGINFO_RISCV64_H
+#define RISU_REGINFO_RISCV64_H
+
+struct reginfo {
+ uint64_t fault_address;
+ uint64_t regs[32];
+ uint64_t fregs[32];
+ uint64_t sp;
+ uint64_t pc;
+ uint32_t flags;
+ uint32_t faulting_insn;
+
+ /* FP */
+ uint32_t fcsr;
+};
+
+#endif /* RISU_REGINFO_RISCV64_H */
--
2.23.0
next prev parent reply other threads:[~2020-04-30 7:24 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 7:21 [RFC PATCH 0/8] RISCV risu porting LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 1/8] riscv: Add RV64I instructions description LIU Zhiwei
2020-05-11 16:39 ` Richard Henderson
2020-05-20 2:41 ` LIU Zhiwei
2020-05-20 5:39 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 2/8] riscv: Generate payload scripts LIU Zhiwei
2020-05-11 17:40 ` Richard Henderson
2020-05-20 2:37 ` LIU Zhiwei
2020-05-20 5:41 ` Richard Henderson
2020-05-20 9:06 ` LIU Zhiwei
2020-04-30 7:21 ` LIU Zhiwei [this message]
2020-05-11 17:42 ` [RFC PATCH 3/8] riscv: Define riscv struct reginfo Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 4/8] riscv: Implement payload load interfaces LIU Zhiwei
2020-05-11 18:03 ` Richard Henderson
2020-05-11 18:07 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 5/8] riscv: Add standard test case LIU Zhiwei
2020-05-11 18:04 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 6/8] riscv: Add configure script LIU Zhiwei
2020-05-11 18:06 ` Richard Henderson
2020-05-20 1:45 ` LIU Zhiwei
2020-05-20 2:28 ` LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 7/8] riscv: Add RV64M instructions description LIU Zhiwei
2020-05-11 18:12 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 8/8] riscv: Add RV64F " LIU Zhiwei
2020-05-11 18:11 ` Richard Henderson
2020-05-19 12:27 ` LIU Zhiwei
2020-05-11 16:30 ` [RFC PATCH 0/8] RISCV risu porting Richard Henderson
2020-05-19 9:44 ` LIU Zhiwei
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