From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: peter.maydell@linaro.org
Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org,
qemu-devel@nongnu.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com, palmer@dabbelt.com,
alistair23@gmail.com, alex.bennee@linaro.org,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [RFC PATCH 5/8] riscv: Add standard test case
Date: Thu, 30 Apr 2020 15:21:36 +0800 [thread overview]
Message-ID: <20200430072139.4602-6-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
test_riscv64.s | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
create mode 100644 test_riscv64.s
diff --git a/test_riscv64.s b/test_riscv64.s
new file mode 100644
index 0000000..5a8279f
--- /dev/null
+++ b/test_riscv64.s
@@ -0,0 +1,85 @@
+/*****************************************************************************
+ * Copyright (c) 2020 PingTouGe Semiconductor
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ * LIU Zhiwei (PingTouGe) - initial implementation
+ * based on test_arm.s by Peter Maydell
+ *****************************************************************************/
+
+/* Initialise the gp regs */
+li x1, 1
+#li x2, 2 # stack pointer
+#li x3, 3 # global pointer
+#li x4, 4 # thread pointer
+li x5, 5
+li x6, 6
+li x7, 7
+li x8, 8
+li x9, 9
+li x10, 10
+li x11, 11
+li x12, 12
+li x13, 13
+li x14, 14
+li x15, 15
+li x16, 16
+li x17, 17
+li x18, 18
+li x19, 19
+li x20, 20
+li x21, 21
+li x22, 22
+li x23, 23
+li x24, 24
+li x25, 25
+li x26, 26
+li x27, 27
+li x28, 28
+li x29, 29
+li x30, 30
+li x31, 30
+
+/* Initialise the fp regs */
+fcvt.d.lu f0, x0
+fcvt.d.lu f1, x1
+#fcvt.d.lu f2, x2
+fcvt.d.lu f3, x3
+fcvt.d.lu f4, x4
+fcvt.d.lu f5, x5
+fcvt.d.lu f6, x6
+fcvt.d.lu f7, x7
+fcvt.d.lu f8, x8
+fcvt.d.lu f9, x9
+fcvt.d.lu f10, x10
+fcvt.d.lu f11, x11
+fcvt.d.lu f12, x12
+fcvt.d.lu f13, x13
+fcvt.d.lu f14, x14
+fcvt.d.lu f15, x15
+fcvt.d.lu f16, x16
+fcvt.d.lu f17, x17
+fcvt.d.lu f18, x18
+fcvt.d.lu f19, x19
+fcvt.d.lu f20, x20
+fcvt.d.lu f21, x21
+fcvt.d.lu f22, x22
+fcvt.d.lu f23, x23
+fcvt.d.lu f24, x24
+fcvt.d.lu f25, x25
+fcvt.d.lu f26, x26
+fcvt.d.lu f27, x27
+fcvt.d.lu f28, x28
+fcvt.d.lu f29, x29
+fcvt.d.lu f30, x30
+fcvt.d.lu f31, x31
+
+/* do compare.
+ * The manual says instr with bits (6:0) == 1 1 0 1 0 1 1 are UNALLOCATED
+ */
+.int 0x0000006b
+/* exit test */
+.int 0x0000016b
--
2.23.0
next prev parent reply other threads:[~2020-04-30 7:24 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 7:21 [RFC PATCH 0/8] RISCV risu porting LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 1/8] riscv: Add RV64I instructions description LIU Zhiwei
2020-05-11 16:39 ` Richard Henderson
2020-05-20 2:41 ` LIU Zhiwei
2020-05-20 5:39 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 2/8] riscv: Generate payload scripts LIU Zhiwei
2020-05-11 17:40 ` Richard Henderson
2020-05-20 2:37 ` LIU Zhiwei
2020-05-20 5:41 ` Richard Henderson
2020-05-20 9:06 ` LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 3/8] riscv: Define riscv struct reginfo LIU Zhiwei
2020-05-11 17:42 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 4/8] riscv: Implement payload load interfaces LIU Zhiwei
2020-05-11 18:03 ` Richard Henderson
2020-05-11 18:07 ` Richard Henderson
2020-04-30 7:21 ` LIU Zhiwei [this message]
2020-05-11 18:04 ` [RFC PATCH 5/8] riscv: Add standard test case Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 6/8] riscv: Add configure script LIU Zhiwei
2020-05-11 18:06 ` Richard Henderson
2020-05-20 1:45 ` LIU Zhiwei
2020-05-20 2:28 ` LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 7/8] riscv: Add RV64M instructions description LIU Zhiwei
2020-05-11 18:12 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 8/8] riscv: Add RV64F " LIU Zhiwei
2020-05-11 18:11 ` Richard Henderson
2020-05-19 12:27 ` LIU Zhiwei
2020-05-11 16:30 ` [RFC PATCH 0/8] RISCV risu porting Richard Henderson
2020-05-19 9:44 ` LIU Zhiwei
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