From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: peter.maydell@linaro.org
Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org,
qemu-devel@nongnu.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com, palmer@dabbelt.com,
alistair23@gmail.com, alex.bennee@linaro.org,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [RFC PATCH 7/8] riscv: Add RV64M instructions description
Date: Thu, 30 Apr 2020 15:21:38 +0800 [thread overview]
Message-ID: <20200430072139.4602-8-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
riscv64.risu | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/riscv64.risu b/riscv64.risu
index 98141ab..f006dc8 100644
--- a/riscv64.risu
+++ b/riscv64.risu
@@ -139,3 +139,46 @@ SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \
SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \
!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 }
+
+@RV64M
+
+MUL RISCV 0000001 rs2:5 rs1:5 000 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULH RISCV 0000001 rs2:5 rs1:5 001 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULHSU RISCV 0000001 rs2:5 rs1:5 010 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULHU RISCV 0000001 rs2:5 rs1:5 011 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIV RISCV 0000001 rs2:5 rs1:5 100 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIVU RISCV 0000001 rs2:5 rs1:5 101 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REM RISCV 0000001 rs2:5 rs1:5 110 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REMU RISCV 0000001 rs2:5 rs1:5 111 rd:5 0110011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+MULW RISCV 0000001 rs2:5 rs1:5 000 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIVW RISCV 0000001 rs2:5 rs1:5 100 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+DIVUW RISCV 0000001 rs2:5 rs1:5 101 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \
+!constraints { $rd != 2 && $rd != 3 && $rd != 4 && $rs1 != 2 && $rs2 != 2 }
+
+
--
2.23.0
next prev parent reply other threads:[~2020-04-30 7:24 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 7:21 [RFC PATCH 0/8] RISCV risu porting LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 1/8] riscv: Add RV64I instructions description LIU Zhiwei
2020-05-11 16:39 ` Richard Henderson
2020-05-20 2:41 ` LIU Zhiwei
2020-05-20 5:39 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 2/8] riscv: Generate payload scripts LIU Zhiwei
2020-05-11 17:40 ` Richard Henderson
2020-05-20 2:37 ` LIU Zhiwei
2020-05-20 5:41 ` Richard Henderson
2020-05-20 9:06 ` LIU Zhiwei
2020-04-30 7:21 ` [RFC PATCH 3/8] riscv: Define riscv struct reginfo LIU Zhiwei
2020-05-11 17:42 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 4/8] riscv: Implement payload load interfaces LIU Zhiwei
2020-05-11 18:03 ` Richard Henderson
2020-05-11 18:07 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 5/8] riscv: Add standard test case LIU Zhiwei
2020-05-11 18:04 ` Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 6/8] riscv: Add configure script LIU Zhiwei
2020-05-11 18:06 ` Richard Henderson
2020-05-20 1:45 ` LIU Zhiwei
2020-05-20 2:28 ` LIU Zhiwei
2020-04-30 7:21 ` LIU Zhiwei [this message]
2020-05-11 18:12 ` [RFC PATCH 7/8] riscv: Add RV64M instructions description Richard Henderson
2020-04-30 7:21 ` [RFC PATCH 8/8] riscv: Add RV64F " LIU Zhiwei
2020-05-11 18:11 ` Richard Henderson
2020-05-19 12:27 ` LIU Zhiwei
2020-05-11 16:30 ` [RFC PATCH 0/8] RISCV risu porting Richard Henderson
2020-05-19 9:44 ` LIU Zhiwei
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