From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Jason Wang" <jasowang@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Tong Ho" <tong.ho@xilinx.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Ramon Fried" <rfried.dev@gmail.com>
Subject: Re: [PATCH v2 03/10] net: cadence_gem: Fix irq update w.r.t queue
Date: Mon, 4 May 2020 16:32:32 +0200 [thread overview]
Message-ID: <20200504143232.GA5519@toto> (raw)
In-Reply-To: <1588601168-27576-4-git-send-email-sai.pavan.boddu@xilinx.com>
On Mon, May 04, 2020 at 07:36:01PM +0530, Sai Pavan Boddu wrote:
> Set irq's specific to a queue, present implementation is setting q1 irq
> based on q0 status.
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> ---
> hw/net/cadence_gem.c | 25 +++----------------------
> 1 file changed, 3 insertions(+), 22 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 6cb2f64..a930bf1 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -554,29 +554,10 @@ static void gem_update_int_status(CadenceGEMState *s)
> {
> int i;
>
> - if (!s->regs[GEM_ISR]) {
> - /* ISR isn't set, clear all the interrupts */
> - for (i = 0; i < s->num_priority_queues; ++i) {
> - qemu_set_irq(s->irq[i], 0);
> - }
> - return;
> - }
> + qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]);
>
> - /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
> - * check it again.
> - */
> - if (s->num_priority_queues == 1) {
> - /* No priority queues, just trigger the interrupt */
> - DB_PRINT("asserting int.\n");
> - qemu_set_irq(s->irq[0], 1);
> - return;
> - }
> -
> - for (i = 0; i < s->num_priority_queues; ++i) {
> - if (s->regs[GEM_INT_Q1_STATUS + i]) {
> - DB_PRINT("asserting int. (q=%d)\n", i);
> - qemu_set_irq(s->irq[i], 1);
> - }
> + for (i = 1; i < s->num_priority_queues; ++i) {
> + qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]);
> }
> }
>
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-05-04 14:52 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-04 14:05 [PATCH v2 00/10] Cadence GEM Fixes Sai Pavan Boddu
2020-05-04 14:05 ` [PATCH v2 01/10] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-04 14:39 ` Edgar E. Iglesias
2020-05-06 9:55 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 02/10] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-04 14:43 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 03/10] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-04 14:32 ` Edgar E. Iglesias [this message]
2020-05-04 14:06 ` [PATCH v2 04/10] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-04 14:57 ` Edgar E. Iglesias
2020-05-06 10:40 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 05/10] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-04 15:02 ` Edgar E. Iglesias
2020-05-06 11:11 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 06/10] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-04 15:23 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 07/10] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-04 15:26 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 08/10] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
2020-05-04 15:27 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 09/10] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-04 15:31 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 10/10] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
2020-05-04 15:33 ` Edgar E. Iglesias
2020-05-04 15:50 ` [PATCH v2 00/10] Cadence GEM Fixes Ramon Fried
2020-05-04 17:15 ` Sai Pavan Boddu
2020-05-05 8:31 ` no-reply
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