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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id h28sm9950916lfe.80.2020.05.04.07.32.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 May 2020 07:32:33 -0700 (PDT) Date: Mon, 4 May 2020 16:32:32 +0200 From: "Edgar E. Iglesias" To: Sai Pavan Boddu Subject: Re: [PATCH v2 03/10] net: cadence_gem: Fix irq update w.r.t queue Message-ID: <20200504143232.GA5519@toto> References: <1588601168-27576-1-git-send-email-sai.pavan.boddu@xilinx.com> <1588601168-27576-4-git-send-email-sai.pavan.boddu@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1588601168-27576-4-git-send-email-sai.pavan.boddu@xilinx.com> User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::243; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x243.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jason Wang , Markus Armbruster , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Tong Ho , Alistair Francis , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Ramon Fried Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, May 04, 2020 at 07:36:01PM +0530, Sai Pavan Boddu wrote: > Set irq's specific to a queue, present implementation is setting q1 irq > based on q0 status. Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Sai Pavan Boddu > --- > hw/net/cadence_gem.c | 25 +++---------------------- > 1 file changed, 3 insertions(+), 22 deletions(-) > > diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c > index 6cb2f64..a930bf1 100644 > --- a/hw/net/cadence_gem.c > +++ b/hw/net/cadence_gem.c > @@ -554,29 +554,10 @@ static void gem_update_int_status(CadenceGEMState *s) > { > int i; > > - if (!s->regs[GEM_ISR]) { > - /* ISR isn't set, clear all the interrupts */ > - for (i = 0; i < s->num_priority_queues; ++i) { > - qemu_set_irq(s->irq[i], 0); > - } > - return; > - } > + qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]); > > - /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to > - * check it again. > - */ > - if (s->num_priority_queues == 1) { > - /* No priority queues, just trigger the interrupt */ > - DB_PRINT("asserting int.\n"); > - qemu_set_irq(s->irq[0], 1); > - return; > - } > - > - for (i = 0; i < s->num_priority_queues; ++i) { > - if (s->regs[GEM_INT_Q1_STATUS + i]) { > - DB_PRINT("asserting int. (q=%d)\n", i); > - qemu_set_irq(s->irq[i], 1); > - } > + for (i = 1; i < s->num_priority_queues; ++i) { > + qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]); > } > } > > -- > 2.7.4 >