From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Jason Wang" <jasowang@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Tong Ho" <tong.ho@xilinx.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Ramon Fried" <rfried.dev@gmail.com>
Subject: Re: [PATCH v2 01/10] net: cadence_gem: Fix debug statements
Date: Mon, 4 May 2020 16:39:22 +0200 [thread overview]
Message-ID: <20200504143922.GB5519@toto> (raw)
In-Reply-To: <1588601168-27576-2-git-send-email-sai.pavan.boddu@xilinx.com>
On Mon, May 04, 2020 at 07:35:59PM +0530, Sai Pavan Boddu wrote:
> Enabling debug breaks the build, Fix them and make debug statements
> always compilable. Fix few statements to use sized integer casting.
>
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> ---
> hw/net/cadence_gem.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 22a0b1b..2f244eb 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -35,14 +35,13 @@
> #include "sysemu/dma.h"
> #include "net/checksum.h"
>
> -#ifdef CADENCE_GEM_ERR_DEBUG
> -#define DB_PRINT(...) do { \
> - fprintf(stderr, ": %s: ", __func__); \
> - fprintf(stderr, ## __VA_ARGS__); \
> - } while (0)
> -#else
> - #define DB_PRINT(...)
> -#endif
> +#define CADENCE_GEM_ERR_DEBUG 0
> +#define DB_PRINT(...) do {\
> + if (CADENCE_GEM_ERR_DEBUG) { \
> + qemu_log(": %s: ", __func__); \
> + qemu_log(__VA_ARGS__); \
> + } \
> +} while (0)
>
> #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */
> #define GEM_NWCFG (0x00000004/4) /* Network Config reg */
> @@ -979,7 +978,8 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
> size += 4;
> }
>
> - DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
> + DB_PRINT("config bufsize: %" PRIu64 " packet size: %" PRIu64 "\n",
> + (uint64_t) rxbufsize, (uint64_t) size);
Shouldn't these be %u and %zd rather than casting to uint64_t?
>
> /* Find which queue we are targeting */
> q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
> @@ -992,9 +992,9 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
> return -1;
> }
>
> - DB_PRINT("copy %u bytes to 0x%" PRIx64 "\n",
> - MIN(bytes_to_copy, rxbufsize),
> - rx_desc_get_buffer(s, s->rx_desc[q]));
> + DB_PRINT("copy %" PRIu32 " bytes to 0x%" PRIx64 "\n",
> + MIN(bytes_to_copy, rxbufsize),
> + rx_desc_get_buffer(s, s->rx_desc[q] + rxbuf_offset));
Looks like this is changing what we print (+ rxbuf_offset), was
that intentional? (it was not mentioned in the commit message)
>
> /* Copy packet data to emulated DMA buffer */
> address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) +
> @@ -1160,8 +1160,8 @@ static void gem_transmit(CadenceGEMState *s)
> */
> if ((tx_desc_get_buffer(s, desc) == 0) ||
> (tx_desc_get_length(desc) == 0)) {
> - DB_PRINT("Invalid TX descriptor @ 0x%x\n",
> - (unsigned)packet_desc_addr);
> + DB_PRINT("Invalid TX descriptor @ 0x%" HWADDR_PRIx "\n",
> + packet_desc_addr);
> break;
> }
>
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-05-04 14:51 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-04 14:05 [PATCH v2 00/10] Cadence GEM Fixes Sai Pavan Boddu
2020-05-04 14:05 ` [PATCH v2 01/10] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-04 14:39 ` Edgar E. Iglesias [this message]
2020-05-06 9:55 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 02/10] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-04 14:43 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 03/10] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-04 14:32 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 04/10] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-04 14:57 ` Edgar E. Iglesias
2020-05-06 10:40 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 05/10] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-04 15:02 ` Edgar E. Iglesias
2020-05-06 11:11 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 06/10] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-04 15:23 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 07/10] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-04 15:26 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 08/10] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
2020-05-04 15:27 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 09/10] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-04 15:31 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 10/10] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
2020-05-04 15:33 ` Edgar E. Iglesias
2020-05-04 15:50 ` [PATCH v2 00/10] Cadence GEM Fixes Ramon Fried
2020-05-04 17:15 ` Sai Pavan Boddu
2020-05-05 8:31 ` no-reply
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