From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Jason Wang" <jasowang@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Tong Ho" <tong.ho@xilinx.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Ramon Fried" <rfried.dev@gmail.com>
Subject: Re: [PATCH v2 02/10] net: cadence_gem: Fix the queue address update during wrap around
Date: Mon, 4 May 2020 16:43:35 +0200 [thread overview]
Message-ID: <20200504144335.GC5519@toto> (raw)
In-Reply-To: <1588601168-27576-3-git-send-email-sai.pavan.boddu@xilinx.com>
On Mon, May 04, 2020 at 07:36:00PM +0530, Sai Pavan Boddu wrote:
> During wrap around and reset, queues are pointing to initial base
> address of queue 0, irrespective of what queue we are dealing with.
> Fix it by assigning proper base address every time.
Might want to add wrappers e.g:
static inline uint32_t gem_get_rx_queue_base_addr(CadenceGEMState *s, int q) {
gem_get_queue_base_addr(s, false, q);
}
static inline uint32_t gem_get_tx_queue_base_addr(CadenceGEMState *s, int q) {
gem_get_queue_base_addr(s, true, q);
}
It makes the packet processing logic a little easier to read, e.g:
s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q);
vs
s->rx_desc_addr[q] = gem_get_queue_base_addr(s, false, q);
Anyway, this looks good to me:
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> ---
> hw/net/cadence_gem.c | 29 +++++++++++++++++++++++++----
> 1 file changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 2f244eb..6cb2f64 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -845,6 +845,25 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
> return 0;
> }
>
> +static uint32_t gem_get_queue_base_addr(CadenceGEMState *s, bool tx, int q)
> +{
> + uint32_t base_addr = 0;
> +
> + switch (q) {
> + case 0:
> + base_addr = s->regs[tx ? GEM_TXQBASE : GEM_RXQBASE];
> + break;
> + case 1 ... (MAX_PRIORITY_QUEUES - 1):
> + base_addr = s->regs[(tx ? GEM_TRANSMIT_Q1_PTR :
> + GEM_RECEIVE_Q1_PTR) + q - 1];
> + break;
> + default:
> + g_assert_not_reached();
> + };
> +
> + return base_addr;
> +}
> +
> static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
> {
> hwaddr desc_addr = 0;
> @@ -1044,7 +1063,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
> /* Next descriptor */
> if (rx_desc_get_wrap(s->rx_desc[q])) {
> DB_PRINT("wrapping RX descriptor list\n");
> - s->rx_desc_addr[q] = s->regs[GEM_RXQBASE];
> + s->rx_desc_addr[q] = gem_get_queue_base_addr(s, false, q);
> } else {
> DB_PRINT("incrementing RX descriptor list\n");
> s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true);
> @@ -1200,7 +1219,8 @@ static void gem_transmit(CadenceGEMState *s)
> sizeof(desc_first));
> /* Advance the hardware current descriptor past this packet */
> if (tx_desc_get_wrap(desc)) {
> - s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
> + s->tx_desc_addr[q] = gem_get_queue_base_addr(s,
> + true, q);
> } else {
> s->tx_desc_addr[q] = packet_desc_addr +
> 4 * gem_get_desc_len(s, false);
> @@ -1252,7 +1272,8 @@ static void gem_transmit(CadenceGEMState *s)
> } else {
> packet_desc_addr = 0;
> }
> - packet_desc_addr |= s->regs[GEM_TXQBASE];
> + packet_desc_addr |= gem_get_queue_base_addr(s,
> + true, q);
> } else {
> packet_desc_addr += 4 * gem_get_desc_len(s, false);
> }
> @@ -1458,7 +1479,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
> if (!(val & GEM_NWCTRL_TXENA)) {
> /* Reset to start of Q when transmit disabled. */
> for (i = 0; i < s->num_priority_queues; i++) {
> - s->tx_desc_addr[i] = s->regs[GEM_TXQBASE];
> + s->tx_desc_addr[i] = gem_get_queue_base_addr(s, true, i);
> }
> }
> if (gem_can_receive(qemu_get_queue(s->nic))) {
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-05-04 14:47 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-04 14:05 [PATCH v2 00/10] Cadence GEM Fixes Sai Pavan Boddu
2020-05-04 14:05 ` [PATCH v2 01/10] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-04 14:39 ` Edgar E. Iglesias
2020-05-06 9:55 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 02/10] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-04 14:43 ` Edgar E. Iglesias [this message]
2020-05-04 14:06 ` [PATCH v2 03/10] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-04 14:32 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 04/10] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-04 14:57 ` Edgar E. Iglesias
2020-05-06 10:40 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 05/10] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-04 15:02 ` Edgar E. Iglesias
2020-05-06 11:11 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 06/10] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-04 15:23 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 07/10] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-04 15:26 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 08/10] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
2020-05-04 15:27 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 09/10] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-04 15:31 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 10/10] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
2020-05-04 15:33 ` Edgar E. Iglesias
2020-05-04 15:50 ` [PATCH v2 00/10] Cadence GEM Fixes Ramon Fried
2020-05-04 17:15 ` Sai Pavan Boddu
2020-05-05 8:31 ` no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200504144335.GC5519@toto \
--to=edgar.iglesias@gmail.com \
--cc=Alistair.Francis@wdc.com \
--cc=armbru@redhat.com \
--cc=jasowang@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=philmd@redhat.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=rfried.dev@gmail.com \
--cc=sai.pavan.boddu@xilinx.com \
--cc=tong.ho@xilinx.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).