From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Jason Wang" <jasowang@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Tong Ho" <tong.ho@xilinx.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Ramon Fried" <rfried.dev@gmail.com>
Subject: Re: [PATCH v2 10/10] net: cadence_gem: Fix RX address filtering
Date: Mon, 4 May 2020 17:33:34 +0200 [thread overview]
Message-ID: <20200504153334.GJ5519@toto> (raw)
In-Reply-To: <1588601168-27576-11-git-send-email-sai.pavan.boddu@xilinx.com>
On Mon, May 04, 2020 at 07:36:08PM +0530, Sai Pavan Boddu wrote:
> From: Tong Ho <tong.ho@xilinx.com>
>
> Two defects are fixed:
>
> 1/ Detection of multicast frames
> 2/ Treating drop of mis-addressed frames as non-error
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Tong Ho <tong.ho@xilinx.com>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> ---
> hw/net/cadence_gem.c | 26 +++++++++++---------------
> 1 file changed, 11 insertions(+), 15 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index f0bf2e7..112794a 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -34,6 +34,7 @@
> #include "qemu/module.h"
> #include "sysemu/dma.h"
> #include "net/checksum.h"
> +#include "net/eth.h"
>
> #define CADENCE_GEM_ERR_DEBUG 0
> #define DB_PRINT(...) do {\
> @@ -669,7 +670,7 @@ static unsigned calc_mac_hash(const uint8_t *mac)
> static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
> {
> uint8_t *gem_spaddr;
> - int i;
> + int i, is_mc;
>
> /* Promiscuous mode? */
> if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
> @@ -685,22 +686,17 @@ static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
> }
>
> /* Accept packets -w- hash match? */
> - if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
> - (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
> + is_mc = is_multicast_ether_addr(packet);
> + if ((is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
> + (!is_mc && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
> + uint64_t buckets;
> unsigned hash_index;
>
> hash_index = calc_mac_hash(packet);
> - if (hash_index < 32) {
> - if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
> - return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
> - GEM_RX_UNICAST_HASH_ACCEPT;
> - }
> - } else {
> - hash_index -= 32;
> - if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
> - return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
> - GEM_RX_UNICAST_HASH_ACCEPT;
> - }
> + buckets = ((uint64_t)s->regs[GEM_HASHHI] << 32) | s->regs[GEM_HASHLO];
> + if ((buckets >> hash_index) & 1) {
> + return is_mc ? GEM_RX_MULTICAST_HASH_ACCEPT
> + : GEM_RX_UNICAST_HASH_ACCEPT;
> }
> }
>
> @@ -924,7 +920,7 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
> /* Is this destination MAC address "for us" ? */
> maf = gem_mac_address_filter(s, buf);
> if (maf == GEM_RX_REJECT) {
> - return -1;
> + return size; /* no, drop siliently b/c it's not an error */
> }
>
> /* Discard packets with receive length error enabled ? */
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-05-04 15:47 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-04 14:05 [PATCH v2 00/10] Cadence GEM Fixes Sai Pavan Boddu
2020-05-04 14:05 ` [PATCH v2 01/10] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-04 14:39 ` Edgar E. Iglesias
2020-05-06 9:55 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 02/10] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-04 14:43 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 03/10] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-04 14:32 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 04/10] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-04 14:57 ` Edgar E. Iglesias
2020-05-06 10:40 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 05/10] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-04 15:02 ` Edgar E. Iglesias
2020-05-06 11:11 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 06/10] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-04 15:23 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 07/10] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-04 15:26 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 08/10] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
2020-05-04 15:27 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 09/10] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-04 15:31 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 10/10] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
2020-05-04 15:33 ` Edgar E. Iglesias [this message]
2020-05-04 15:50 ` [PATCH v2 00/10] Cadence GEM Fixes Ramon Fried
2020-05-04 17:15 ` Sai Pavan Boddu
2020-05-05 8:31 ` no-reply
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