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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id m3sm2154818wrn.96.2020.05.11.06.34.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2020 06:34:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 00/34] target-arm queue Date: Mon, 11 May 2020 14:33:31 +0100 Message-Id: <20200511133405.5275-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit c88f1ffc19e38008a1c33ae039482a860aa7418c: Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2020-05-08 14:29:18 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200511 for you to fetch changes up to 7e17d50ebd359ee5fa3d65d7fdc0fe0336d60694: target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) (2020-05-11 14:22:54 +0100) ---------------------------------------------------------------- target-arm queue: aspeed: Add boot stub for smp booting target/arm: Drop access_el3_aa32ns_aa64any() aspeed: Support AST2600A1 silicon revision aspeed: sdmc: Implement AST2600 locking behaviour nrf51: Tracing cleanups target/arm: Improve handling of SVE loads and stores target/arm: Don't show TCG-only CPUs in KVM-only QEMU builds hw/arm/musicpal: Map the UART devices unconditionally target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA ---------------------------------------------------------------- Edgar E. Iglesias (1): target/arm: Drop access_el3_aa32ns_aa64any() Joel Stanley (3): aspeed: Add boot stub for smp booting aspeed: Support AST2600A1 silicon revision aspeed: sdmc: Implement AST2600 locking behaviour Philippe Mathieu-Daudé (8): hw/arm/nrf51: Add NRF51_PERIPHERAL_SIZE definition hw/timer/nrf51_timer: Display timer ID in trace events hw/timer/nrf51_timer: Add trace event of counter value update target/arm/kvm: Inline set_feature() calls target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[] target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs target/arm: Restrict TCG cpus to TCG accel hw/arm/musicpal: Map the UART devices unconditionally Richard Henderson (21): exec: Add block comments for watchpoint routines exec: Fix cpu_watchpoint_address_matches address length accel/tcg: Add block comment for probe_access accel/tcg: Adjust probe_access call to page_check_range accel/tcg: Add probe_access_flags accel/tcg: Add endian-specific cpu_{ld, st}* operations target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn target/arm: Drop manual handling of set/clear_helper_retaddr target/arm: Add sve infrastructure for page lookup target/arm: Adjust interface of sve_ld1_host_fn target/arm: Use SVEContLdSt in sve_ld1_r target/arm: Handle watchpoints in sve_ld1_r target/arm: Use SVEContLdSt for multi-register contiguous loads target/arm: Update contiguous first-fault and no-fault loads target/arm: Use SVEContLdSt for contiguous stores target/arm: Reuse sve_probe_page for gather first-fault loads target/arm: Reuse sve_probe_page for scatter stores target/arm: Reuse sve_probe_page for gather loads target/arm: Remove sve_memopidx target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) Thomas Huth (1): target/arm: Make set_feature() available for other files docs/devel/loads-stores.rst | 39 +- include/exec/cpu-all.h | 13 +- include/exec/cpu_ldst.h | 283 +++-- include/exec/exec-all.h | 39 + include/hw/arm/nrf51.h | 3 +- include/hw/core/cpu.h | 23 + include/hw/i2c/microbit_i2c.h | 2 +- include/hw/misc/aspeed_scu.h | 1 + include/hw/timer/nrf51_timer.h | 1 + target/arm/cpu.h | 10 + target/arm/helper-sve.h | 45 +- target/arm/internals.h | 5 - accel/tcg/cputlb.c | 413 ++++--- accel/tcg/user-exec.c | 256 ++++- exec.c | 2 +- hw/arm/aspeed.c | 73 +- hw/arm/aspeed_ast2600.c | 6 +- hw/arm/musicpal.c | 12 +- hw/arm/nrf51_soc.c | 9 +- hw/i2c/microbit_i2c.c | 2 +- hw/misc/aspeed_scu.c | 11 +- hw/misc/aspeed_sdmc.c | 55 +- hw/timer/nrf51_timer.c | 14 +- target/arm/cpu.c | 662 +---------- target/arm/cpu64.c | 18 +- target/arm/cpu_tcg.c | 664 +++++++++++ target/arm/helper.c | 30 +- target/arm/kvm32.c | 13 +- target/arm/kvm64.c | 22 +- target/arm/sve_helper.c | 2398 +++++++++++++++++++++------------------- target/arm/translate-sve.c | 93 +- hw/timer/trace-events | 5 +- target/arm/Makefile.objs | 1 + 33 files changed, 2975 insertions(+), 2248 deletions(-) create mode 100644 target/arm/cpu_tcg.c