From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 11/17] target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree
Date: Tue, 12 May 2020 17:38:58 +0100 [thread overview]
Message-ID: <20200512163904.10918-12-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org>
Convert the Neon VADD, VSUB, VABD 3-reg-same insns to decodetree.
We already have gvec helpers for addition and subtraction, but must
add one for fabd.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.h | 3 ++-
target/arm/neon-dp.decode | 8 ++++++++
target/arm/neon_helper.c | 7 -------
target/arm/translate-neon.inc.c | 28 ++++++++++++++++++++++++++++
target/arm/translate.c | 10 +++-------
target/arm/vec_helper.c | 7 +++++++
6 files changed, 48 insertions(+), 15 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 1857f4ee46a..6e9629c87b0 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -396,7 +396,6 @@ DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32)
DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32)
DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64)
-DEF_HELPER_3(neon_abd_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr)
DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr)
@@ -595,6 +594,8 @@ DEF_HELPER_FLAGS_5(gvec_fmul_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_fmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_fmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fabd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_5(gvec_ftsmul_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_ftsmul_s, TCG_CALL_NO_RWG,
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index 28e8333335d..06fb8b96aad 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -45,6 +45,10 @@
@3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
+# For FP insns the high bit of 'size' is used as part of opcode decode
+@3same_fp .... ... . . . . size:1 .... .... .... . q:1 . . .... \
+ &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
@@ -170,3 +174,7 @@ SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp
VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same
+
+VADD_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 0 .... @3same_fp
+VSUB_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
+VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp
diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c
index 2ef75e04c83..b637265691a 100644
--- a/target/arm/neon_helper.c
+++ b/target/arm/neon_helper.c
@@ -1825,13 +1825,6 @@ uint64_t HELPER(neon_qneg_s64)(CPUARMState *env, uint64_t x)
}
/* NEON Float helpers. */
-uint32_t HELPER(neon_abd_f32)(uint32_t a, uint32_t b, void *fpstp)
-{
- float_status *fpst = fpstp;
- float32 f0 = make_float32(a);
- float32 f1 = make_float32(b);
- return float32_val(float32_abs(float32_sub(f0, f1, fpst)));
-}
/* Floating point comparisons produce an integer result.
* Note that EQ doesn't signal InvalidOp for QNaNs but GE and GT do.
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index f52302f42b1..540720f5e0d 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -1021,3 +1021,31 @@ DO_3SAME_PAIR(VPADD, padd_u)
DO_3SAME_VQDMULH(VQDMULH, qdmulh)
DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)
+
+/*
+ * For all the functions using this macro, size == 1 means fp16,
+ * which is an architecture extension we don't implement yet.
+ */
+#define DO_3S_FP_GVEC(INSN,FUNC) \
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rn_ofs, uint32_t rm_ofs, \
+ uint32_t oprsz, uint32_t maxsz) \
+ { \
+ TCGv_ptr fpst = get_fpstatus_ptr(1); \
+ tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpst, \
+ oprsz, maxsz, 0, FUNC); \
+ tcg_temp_free_ptr(fpst); \
+ } \
+ static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (a->size != 0) { \
+ /* TODO fp16 support */ \
+ return false; \
+ } \
+ return do_3same(s, a, gen_##INSN##_3s); \
+ }
+
+
+DO_3S_FP_GVEC(VADD, gen_helper_gvec_fadd_s)
+DO_3S_FP_GVEC(VSUB, gen_helper_gvec_fsub_s)
+DO_3S_FP_GVEC(VABD, gen_helper_gvec_fabd_s)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 561cb67286d..8a94856cd28 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5445,6 +5445,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
switch (op) {
case NEON_3R_FLOAT_ARITH:
pairwise = (u && size < 2); /* if VPADD (float) */
+ if (!pairwise) {
+ return 1; /* handled by decodetree */
+ }
break;
case NEON_3R_FLOAT_MINMAX:
pairwise = u; /* if VPMIN/VPMAX (float) */
@@ -5501,16 +5504,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
{
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
switch ((u << 2) | size) {
- case 0: /* VADD */
case 4: /* VPADD */
gen_helper_vfp_adds(tmp, tmp, tmp2, fpstatus);
break;
- case 2: /* VSUB */
- gen_helper_vfp_subs(tmp, tmp, tmp2, fpstatus);
- break;
- case 6: /* VABD */
- gen_helper_neon_abd_f32(tmp, tmp, tmp2, fpstatus);
- break;
default:
abort();
}
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index fa33df859e5..50a499299fd 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -691,6 +691,11 @@ static float64 float64_ftsmul(float64 op1, uint64_t op2, float_status *stat)
return result;
}
+static float32 float32_abd(float32 op1, float32 op2, float_status *stat)
+{
+ return float32_abs(float32_sub(op1, op2, stat));
+}
+
#define DO_3OP(NAME, FUNC, TYPE) \
void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
{ \
@@ -718,6 +723,8 @@ DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16)
DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32)
DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64)
+DO_3OP(gvec_fabd_s, float32_abd, float32)
+
#ifdef TARGET_AARCH64
DO_3OP(gvec_recps_h, helper_recpsf_f16, float16)
--
2.20.1
next prev parent reply other threads:[~2020-05-12 16:52 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-12 16:38 [PATCH v2 00/17] target/arm: Convert rest of Neon 3-reg-same to decodetree Peter Maydell
2020-05-12 16:38 ` [PATCH v2 01/17] target/arm: Convert Neon 3-reg-same VQRDMLAH/VQRDMLSH " Peter Maydell
2020-05-13 16:39 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 02/17] target/arm: Convert Neon 3-reg-same SHA " Peter Maydell
2020-05-12 16:38 ` [PATCH v2 03/17] target/arm: Convert Neon 64-bit element 3-reg-same insns Peter Maydell
2020-05-13 20:27 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 04/17] target/arm: Convert Neon VHADD " Peter Maydell
2020-05-13 16:47 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 05/17] target/arm: Convert Neon VABA/VABD 3-reg-same to decodetree Peter Maydell
2020-05-13 16:48 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 06/17] target/arm: Convert Neon VRHADD, VHSUB 3-reg-same insns " Peter Maydell
2020-05-13 16:50 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 07/17] target/arm: Convert Neon VQSHL, VRSHL, VQRSHL " Peter Maydell
2020-05-13 16:55 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 08/17] target/arm: Convert Neon VPMAX/VPMIN " Peter Maydell
2020-05-12 16:38 ` [PATCH v2 09/17] target/arm: Convert Neon VPADD " Peter Maydell
2020-05-12 16:38 ` [PATCH v2 10/17] target/arm: Convert Neon VQDMULH/VQRDMULH 3-reg-same " Peter Maydell
2020-05-13 16:58 ` Richard Henderson
2020-05-12 16:38 ` Peter Maydell [this message]
2020-05-13 20:06 ` [PATCH v2 11/17] target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns " Richard Henderson
2020-05-12 16:38 ` [PATCH v2 12/17] target/arm: Convert Neon VPMIN/VPMAX/VPADD float " Peter Maydell
2020-05-12 16:39 ` [PATCH v2 13/17] target/arm: Convert Neon fp VMUL, VMLA, VMLS " Peter Maydell
2020-05-13 20:28 ` Richard Henderson
2020-05-12 16:39 ` [PATCH v2 14/17] target/arm: Convert Neon 3-reg-same compare " Peter Maydell
2020-05-12 16:39 ` [PATCH v2 15/17] target/arm: Move 'env' argument of recps_f32 and rsqrts_f32 helpers to usual place Peter Maydell
2020-05-13 20:16 ` Richard Henderson
2020-05-12 16:39 ` [PATCH v2 16/17] target/arm: Convert Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS to decodetree Peter Maydell
2020-05-13 20:20 ` Richard Henderson
2020-05-12 16:39 ` [PATCH v2 17/17] target/arm: Convert NEON VFMA, VFMS 3-reg-same insns " Peter Maydell
2020-05-12 23:44 ` [PATCH v2 00/17] target/arm: Convert rest of Neon 3-reg-same " no-reply
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