From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v2 06/17] target/arm: Convert Neon VRHADD, VHSUB 3-reg-same insns to decodetree
Date: Tue, 12 May 2020 17:38:53 +0100 [thread overview]
Message-ID: <20200512163904.10918-7-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200512163904.10918-1-peter.maydell@linaro.org>
Convert the Neon VRHADD and VHSUB 3-reg-same insns to decodetree.
(These are all the other insns in 3-reg-same which were using
GEN_NEON_INTEGER_OP() and which are not pairwise or
reversed-operands.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/neon-dp.decode | 6 ++++++
target/arm/translate-neon.inc.c | 4 ++++
target/arm/translate.c | 8 ++------
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index 25c08a4170d..353cb1f4992 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -47,6 +47,9 @@ VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
+VRHADD_S_3s 1111 001 0 0 . .. .... .... 0001 . . . 0 .... @3same
+VRHADD_U_3s 1111 001 1 0 . .. .... .... 0001 . . . 0 .... @3same
+
@3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
@@ -59,6 +62,9 @@ VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
+VHSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 0 .... @3same
+VHSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 0 .... @3same
+
VQSUB_S_3s 1111 001 0 0 . .. .... .... 0010 . . . 1 .... @3same
VQSUB_U_3s 1111 001 1 0 . .. .... .... 0010 . . . 1 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index 20f0f2c8d83..e9da47171c6 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -877,3 +877,7 @@ DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64)
DO_3SAME_32(VHADD_S, hadd_s)
DO_3SAME_32(VHADD_U, hadd_u)
+DO_3SAME_32(VHSUB_S, hsub_s)
+DO_3SAME_32(VHSUB_U, hsub_u)
+DO_3SAME_32(VRHADD_S, rhadd_s)
+DO_3SAME_32(VRHADD_U, rhadd_u)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2c842df4451..ebb899d846e 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5435,6 +5435,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_3R_VSHL:
case NEON_3R_SHA:
case NEON_3R_VHADD:
+ case NEON_3R_VRHADD:
+ case NEON_3R_VHSUB:
case NEON_3R_VABD:
case NEON_3R_VABA:
/* Already handled by decodetree */
@@ -5517,12 +5519,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tmp2 = neon_load_reg(rm, pass);
}
switch (op) {
- case NEON_3R_VRHADD:
- GEN_NEON_INTEGER_OP(rhadd);
- break;
- case NEON_3R_VHSUB:
- GEN_NEON_INTEGER_OP(hsub);
- break;
case NEON_3R_VQSHL:
GEN_NEON_INTEGER_OP_ENV(qshl);
break;
--
2.20.1
next prev parent reply other threads:[~2020-05-12 16:47 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-12 16:38 [PATCH v2 00/17] target/arm: Convert rest of Neon 3-reg-same to decodetree Peter Maydell
2020-05-12 16:38 ` [PATCH v2 01/17] target/arm: Convert Neon 3-reg-same VQRDMLAH/VQRDMLSH " Peter Maydell
2020-05-13 16:39 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 02/17] target/arm: Convert Neon 3-reg-same SHA " Peter Maydell
2020-05-12 16:38 ` [PATCH v2 03/17] target/arm: Convert Neon 64-bit element 3-reg-same insns Peter Maydell
2020-05-13 20:27 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 04/17] target/arm: Convert Neon VHADD " Peter Maydell
2020-05-13 16:47 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 05/17] target/arm: Convert Neon VABA/VABD 3-reg-same to decodetree Peter Maydell
2020-05-13 16:48 ` Richard Henderson
2020-05-12 16:38 ` Peter Maydell [this message]
2020-05-13 16:50 ` [PATCH v2 06/17] target/arm: Convert Neon VRHADD, VHSUB 3-reg-same insns " Richard Henderson
2020-05-12 16:38 ` [PATCH v2 07/17] target/arm: Convert Neon VQSHL, VRSHL, VQRSHL " Peter Maydell
2020-05-13 16:55 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 08/17] target/arm: Convert Neon VPMAX/VPMIN " Peter Maydell
2020-05-12 16:38 ` [PATCH v2 09/17] target/arm: Convert Neon VPADD " Peter Maydell
2020-05-12 16:38 ` [PATCH v2 10/17] target/arm: Convert Neon VQDMULH/VQRDMULH 3-reg-same " Peter Maydell
2020-05-13 16:58 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 11/17] target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns " Peter Maydell
2020-05-13 20:06 ` Richard Henderson
2020-05-12 16:38 ` [PATCH v2 12/17] target/arm: Convert Neon VPMIN/VPMAX/VPADD float " Peter Maydell
2020-05-12 16:39 ` [PATCH v2 13/17] target/arm: Convert Neon fp VMUL, VMLA, VMLS " Peter Maydell
2020-05-13 20:28 ` Richard Henderson
2020-05-12 16:39 ` [PATCH v2 14/17] target/arm: Convert Neon 3-reg-same compare " Peter Maydell
2020-05-12 16:39 ` [PATCH v2 15/17] target/arm: Move 'env' argument of recps_f32 and rsqrts_f32 helpers to usual place Peter Maydell
2020-05-13 20:16 ` Richard Henderson
2020-05-12 16:39 ` [PATCH v2 16/17] target/arm: Convert Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS to decodetree Peter Maydell
2020-05-13 20:20 ` Richard Henderson
2020-05-12 16:39 ` [PATCH v2 17/17] target/arm: Convert NEON VFMA, VFMS 3-reg-same insns " Peter Maydell
2020-05-12 23:44 ` [PATCH v2 00/17] target/arm: Convert rest of Neon 3-reg-same " no-reply
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