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s=201602; t=1589364573; bh=ycRgYu/A8+K8wasjeVvJsGvRyawu+F1RnpdIZE8PkgA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=BFrIpfJAEVhpw8ls1WyMOSYQ9XlIOO0rTRHQsanU74FINFoDBMFPzK88b5y+n9Oaz /qwcHWhYGgmEViTZyAkIOovIBcauc9GM/eijEXW1/f8i3lqnw2M8jI57dAmCpYpUIv dB/W6ynfw1dq9gKyJ8+GlNh0ULiTPyBS2PZlchtY= Date: Wed, 13 May 2020 15:56:54 +1000 From: David Gibson To: =?iso-8859-1?Q?C=E9dric?= Le Goater Subject: Re: [PATCH] ppc/pnv: Add definitions for interrupts occurring in power-saving mode Message-ID: <20200513055654.GA2183@umbus.fritz.box> References: <20200511085822.65319-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="Ca0/yK2c6QcOc1Rp" Content-Disposition: inline In-Reply-To: <20200511085822.65319-1-clg@kaod.org> Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/13 06:09:35 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_03_06=1.592, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Nicholas Piggin Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --Ca0/yK2c6QcOc1Rp Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, May 11, 2020 at 10:58:22AM +0200, C=E9dric Le Goater wrote: > If an interrupt occurred when the thread was in power-saving mode, > bits [42:45] of SRR1 indicate the exception that caused exit from > power-saving mode. >=20 > bits [46:47] of SRR1 indicate the power-saving mode in which the > thread was when the interrupt occured. >=20 > Signed-off-by: C=E9dric Le Goater Applied to ppc-for-5.1. > --- > target/ppc/cpu.h | 21 +++++++++++++++++++++ > hw/ppc/pnv.c | 8 ++++---- > target/ppc/excp_helper.c | 16 ++++++++-------- > 3 files changed, 33 insertions(+), 12 deletions(-) >=20 > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index df5c30160da8..9648623677d2 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -476,6 +476,27 @@ typedef struct ppc_v3_pate_t { > #define SRR1_PROTFAULT DSISR_PROTFAULT > #define SRR1_IAMR DSISR_AMR > =20 > +/* SRR1[42:45] wakeup fields for System Reset Interrupt */ > + > +#define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */ > + > +#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */ > +#define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt= (P9) */ > +#define SRR1_WAKEEE 0x00200000 /* External interrupt */ > +#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */ > +#define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */ > +#define SRR1_WAKERESET 0x00100000 /* System reset */ > +#define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */ > +#define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving m= ode */ > + > +/* SRR1[46:47] power-saving exit mode */ > + > +#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */ > + > +#define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintaine= d */ > +#define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */ > +#define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */ > + > /* Facility Status and Control (FSCR) bits */ > #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */ > #define FSCR_TAR (63 - 55) /* Target Address Register */ > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 1b4748ce6dc3..182b62565022 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1986,15 +1986,15 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, r= un_on_cpu_data arg) > =20 > cpu_synchronize_state(cs); > ppc_cpu_do_system_reset(cs); > - if (env->spr[SPR_SRR1] & PPC_BITMASK(46, 47)) { > + if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { > /* > * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the > * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 > * (PPC_BIT(43)). > */ > - if (!(env->spr[SPR_SRR1] & PPC_BIT(43))) { > + if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { > warn_report("ppc_cpu_do_system_reset does not set system res= et wakeup reason"); > - env->spr[SPR_SRR1] |=3D PPC_BIT(43); > + env->spr[SPR_SRR1] |=3D SRR1_WAKERESET; > } > } else { > /* > @@ -2004,7 +2004,7 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run= _on_cpu_data arg) > * another CPU requesting a NMI IPI) system reset exception should be > * 0b0010 (PPC_BIT(44)). > */ > - env->spr[SPR_SRR1] |=3D PPC_BIT(44); > + env->spr[SPR_SRR1] |=3D SRR1_WAKESCOM; > } > } > =20 > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c > index 14d39029825a..a988ba15f4f7 100644 > --- a/target/ppc/excp_helper.c > +++ b/target/ppc/excp_helper.c > @@ -101,7 +101,7 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPPCS= tate *env, int excp, > env->resume_as_sreset =3D false; > =20 > /* Pretend to be returning from doze always as we don't lose state */ > - *msr |=3D (0x1ull << (63 - 47)); > + *msr |=3D SRR1_WS_NOLOSS; > =20 > /* Machine checks are sent normally */ > if (excp =3D=3D POWERPC_EXCP_MCHECK) { > @@ -109,25 +109,25 @@ static int powerpc_reset_wakeup(CPUState *cs, CPUPP= CState *env, int excp, > } > switch (excp) { > case POWERPC_EXCP_RESET: > - *msr |=3D 0x4ull << (63 - 45); > + *msr |=3D SRR1_WAKERESET; > break; > case POWERPC_EXCP_EXTERNAL: > - *msr |=3D 0x8ull << (63 - 45); > + *msr |=3D SRR1_WAKEEE; > break; > case POWERPC_EXCP_DECR: > - *msr |=3D 0x6ull << (63 - 45); > + *msr |=3D SRR1_WAKEDEC; > break; > case POWERPC_EXCP_SDOOR: > - *msr |=3D 0x5ull << (63 - 45); > + *msr |=3D SRR1_WAKEDBELL; > break; > case POWERPC_EXCP_SDOOR_HV: > - *msr |=3D 0x3ull << (63 - 45); > + *msr |=3D SRR1_WAKEHDBELL; > break; > case POWERPC_EXCP_HV_MAINT: > - *msr |=3D 0xaull << (63 - 45); > + *msr |=3D SRR1_WAKEHMI; > break; > case POWERPC_EXCP_HVIRT: > - *msr |=3D 0x9ull << (63 - 45); > + *msr |=3D SRR1_WAKEHVI; > break; > default: > cpu_abort(cs, "Unsupported exception %d in Power Save mode\n", --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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