From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PATCH v4 04/16] target/arm: Remove unnecessary range check for VSHL
Date: Wed, 13 May 2020 09:32:33 -0700 [thread overview]
Message-ID: <20200513163245.17915-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200513163245.17915-1-richard.henderson@linaro.org>
In 1dc8425e551, while converting to gvec, I added an extra range check
against the shift count. This was unnecessary because the encoding of
the shift count produces 0 to the element size - 1.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 3c489852dc..2eec689c5e 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5752,16 +5752,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
gen_gvec_sli(size, rd_ofs, rm_ofs, shift,
vec_size, vec_size);
} else { /* VSHL */
- /* Shifts larger than the element size are
- * architecturally valid and results in zero.
- */
- if (shift >= 8 << size) {
- tcg_gen_gvec_dup_imm(size, rd_ofs,
- vec_size, vec_size, 0);
- } else {
- tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
- vec_size, vec_size);
- }
+ tcg_gen_gvec_shli(size, rd_ofs, rm_ofs, shift,
+ vec_size, vec_size);
}
return 0;
}
--
2.20.1
next prev parent reply other threads:[~2020-05-13 16:39 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 16:32 [PATCH v4 00/16] target/arm: partial vector cleanup Richard Henderson
2020-05-13 16:32 ` [PATCH v4 01/16] target/arm: Create gen_gvec_[us]sra Richard Henderson
2020-05-13 16:32 ` [PATCH v4 02/16] target/arm: Create gen_gvec_{u,s}{rshr,rsra} Richard Henderson
2020-05-13 16:32 ` [PATCH v4 03/16] target/arm: Create gen_gvec_{sri,sli} Richard Henderson
2020-05-13 16:32 ` Richard Henderson [this message]
2020-05-13 16:32 ` [PATCH v4 05/16] target/arm: Tidy handle_vec_simd_shri Richard Henderson
2020-05-13 16:32 ` [PATCH v4 06/16] target/arm: Create gen_gvec_{ceq,clt,cle,cgt,cge}0 Richard Henderson
2020-05-13 16:32 ` [PATCH v4 07/16] target/arm: Create gen_gvec_{mla,mls} Richard Henderson
2020-05-13 16:32 ` [PATCH v4 08/16] target/arm: Swap argument order for VSHL during decode Richard Henderson
2020-05-13 16:32 ` [PATCH v4 09/16] target/arm: Create gen_gvec_{cmtst,ushl,sshl} Richard Henderson
2020-05-13 16:32 ` [PATCH v4 10/16] target/arm: Create gen_gvec_{uqadd, sqadd, uqsub, sqsub} Richard Henderson
2020-05-13 16:32 ` [PATCH v4 11/16] target/arm: Remove fp_status from helper_{recpe, rsqrte}_u32 Richard Henderson
2020-05-13 16:32 ` [PATCH v4 12/16] target/arm: Create gen_gvec_{qrdmla,qrdmls} Richard Henderson
2020-05-13 16:32 ` [PATCH v4 13/16] target/arm: Pass pointer to qc to qrdmla/qrdmls Richard Henderson
2020-05-13 16:32 ` [PATCH v4 14/16] target/arm: Clear tail in gvec_fmul_idx_*, gvec_fmla_idx_* Richard Henderson
2020-05-13 16:32 ` [PATCH v4 15/16] target/arm: Vectorize SABD/UABD Richard Henderson
2020-05-13 16:32 ` [PATCH v4 16/16] target/arm: Vectorize SABA/UABA Richard Henderson
2020-05-14 10:27 ` [PATCH v4 00/16] target/arm: partial vector cleanup Peter Maydell
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